As if building and compensating a wideband transimpedance amplifier
for photodiode applications weren't challenging enough, measuring the
amplifier's ac performance independently of the photodiode also presents
a considerable hurdle. Often, the photodiode intended for the application
has its own frequency response. In addition, if the photodiode is used
to evaluate the amplifier, the technique used for injecting an optical
signal into the photodiode may introduce an unknown frequency response.
To circumvent these problems and observe just the performance of the
transimpedance amplifier itself, you can use a network analyzer source
connected to the simple interface circuit described here. This passive
circuit will deliver a low-level current signal from a capacitive source
impedance, thus emulating the photodiode signal current and capacitance
to the amplifier circuit.
The test interface circuit from the network analyzer to the transimpedance
amplifier under test is shown (Fig. 1). Capacitor C2 would
connect into the input of the transimpedance gain stage. If this is implemented
using a high-open-loop-gain operational amplifier, the test current (Id)
will drive into a low impedance virtual ground. Intuitively, both C1 and
C2 short out at high frequencies and the network analyzer simply delivers
a current into the 50-Ω
input-matching resistor, Rs.
On the other side of the matching resistor, that current splits between
the two capacitors, with most of it going through C1 when C1>>C2.
Continuing the assumption that C1 >> C2, and looking back toward
C2 from the transimpedance gain stage, it will simply see a capacitive
source impedance equal to C2 as C1 shorts to ground and both impedances
become less than the resistive source impedances.
Continuing the assumption that C2 is feeding into a virtual ground,
the Laplace transfer function for the transconductance from Vs
to Id for the interface circuit of Figure 1 may be written
as:
This equation shows a zero at dc and a high-frequency pole at 1/2¼(2Rs(C1
+ C2)) Hz. At dc, there is no signal current injected through C2. The
test current, Id, increases with frequency until the pole frequency.
Beyond this, a constant current set by the transconductance from the Vs
source to Id, 1/(2R(1+C2/C1)), is delivered through C2. Equation
2 gives the Laplace expression for the output impedance looking back from
the transimpedance gain stage towards C2.
The source impedance for the test interface circuit starts out at infinity
at dc, decreasing with frequency due to the first pole at s = 0 until
it reaches a zero that occurs at the same frequency as the pole in the
transconductance shown in Equation 1. This source impedance then goes
through another pole at 1/2¼(2RsC1) Hz. This causes the
source impedance to look like a capacitor equal to the series combination
of C1 and C2 above that corner frequency.
Although this zero/pole pair in the source impedance doesn't exactly
match the simple source capacitance of a photodiode detector, the key
requirement is that it look capacitive at frequencies on the order of
the closed-loop transimpedance bandwidth for the amplifier under test.
When C1>> C2, the zero/pole pair in Equation 2 cancels each other
giving just the desired capacitive source impedance equal to the series
combination of C1 and C2.
With C1>>C2, the source capacitance for the transimpedance stage
will be nearly equal to C2. This will constrain C2 to equal the expected
photodiode capacitance (Cd) that the circuit is intended to
emulate. With the input resistor, Rs, set to match the network
analyzer's source impedance (normally 50 Ω),
only C1 remains to be set. The value for C1 will determine both the low
frequency corner for the current delivered through C2 (where it goes flat
with frequency) and the transconducstance from Vs to Id--neither
of which are critical.
One important parasitic does need to be considered before setting C1.
Capacitor C1 may go through self-resonance due to its series inductance
prior to the expected corner frequency of the completed transimpedance
amplifier under test. The resulting increase in the current delivered
through C2 can obscure the actual roll-off frequency for the amplifier.
This suggests that the value for C1 be set to give a self resonant frequency
much higher than the expected closed-loop transimpedance bandwidth.
However, decreasing C1 to move this self-resonant frequency up also
increases the pole frequency for the transconductance from Vs
to Id. Capacitor C1 must be set to balance the requirement
to bring Id flat with frequency well before the anticipated
transimpedance bandwidth. This suggests a high C1 value; but, C1 must
be low enough in value to move its own self-resonance well beyond the
test frequency range of interest.
To show the constraints that will lead to a solution for C1, consider
Figure 2. This diagram shows the input interface feeding into an
op-amp transimpedance amplifier where the op amp has a gain bandwidth
product equal to GBP (in Hz).
To use this test interface circuit, while minimizing the interaction
with L1, set the self resonant frequency, Fr, as given in Equation
3.
In this equation, F-3dB is the anticipated transimpedance
bandwidth and ß is the ratio of the self-resonant frequency to F-3dB.
One useful design point for setting the transimpedance compensation
is to set Cf to give a maximally-flat Butterworth closed-loop
frequency response. This can be achieved by setting:
In Equation 5, Cs is the total capacitance on the inverting
op-amp pin, which is equal to (C1C2/(C1+C2)) + Cp, where Cp
equals the op-amp input capacitance.
In this analysis, we are simply trying to set C1 approximately, in order
to measure the high-frequency roll-off of the transimpedance amplifier.
So, approximate Cs = C2 in the equation for Fo in
the analysis to get C1. However, the total value for Cs (including
the op-amp input parasitics) will need to be used in setting Cf
for the correct compensation.
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