[Design Application]
High Integration Simplifies Signal Processing For CCDs
CMOS ICs Offer Complete Analog Signal Processing For CCD Imaging To Lower Overall Cost, Power Consumption, And Size.
The charge-coupled device (CCD) is the image sensor of choice for most consumer-oriented imaging applications. Traditionally, the device's unique analog signal-processing chain has been implemented using standard linear components—op-amps, analog-to-digital and digital-to-analog converters (ADCs and DACs, respectively), analog multipliers, and analog switches. Recent advances in semiconductor design and technology have allowed a number of companies to introduce a single integrated circuit (IC) to handle all of the signal-processing steps required, from the CCD output right through the analog-to-digital conversion. The devices retain the performance of traditional designs, yet provide substantial savings in cost, power, and size. Before taking full advantage of these devices however, it is important to fully understand what they can and cannot do.
The markets for scanners, digital still cameras (DSC), and camcorders have become extremely competitive. In all three, prices are falling as the imaging companies compete for market share. Typically, consumers demand that each new generation of products offer higher performance for the same price as previous models, or at least give comparable performance at a lower cost. With cameras in particular, smaller size and longer battery life are key selling points.
For semiconductor manufacturers, this means that the 8-bit ADC that was adequate for low-end scanners in the past, is now being replaced by a 10-bit converter. With camcorder and DSC applications moving to higher-resolution CCD arrays with higher pixel rates, these same manufacturers must produce the analog processing circuitry required to operate at the higher sampling rates needed to maintain proper readout times and frame rates.
Semiconductor companies are now offering integrated solutions for CCD signal processing that combine all of the necessary front-end analog circuitry. Although this yields an obvious reduction in size and potential cost savings, high integration alone will not help designers meet all of the consumer's requirements. To help the designer more effectively address all of their needs, these devices are being implemented using low-cost, low-power, standard CMOS processes. This approach is possible because semiconductor companies have improved their capabilities in CMOS analog circuitry, eliminating the need for proven, but costlier BiCMOS and bipolar implementations. The remaining challenge for the semiconductor companies is to achieve the performance level required for the different imaging applications.
Processing The Signal To understand what the integrated signal processing components have to offer, consider the typical CCD output waveform (Fig. 1). One period of this signal consists of a reset feedthrough level, a reference level, and a data level. The voltage difference between the reference and the data levels contains the light information for an individual pixel. To accurately process and digitize the CCD signal, the integrated signal processing components perform several basic operations. These are: correlated double sampling (CDS), dc restoration (clamping), gain, offset, and analog-to-digital conversion.
CDS is one of the most important steps in processing the CCD waveform. The operation serves two important purposes: it calculates the difference between the reference and data levels of the CCD signal, and it reduces some of the noise components in the CCD signal. Conceptually, the CDS is a differential-in-time amplifier, because it takes two separate samples of the input signal and outputs the difference between them (Fig. 2). There are varied topologies being used to perform this operation.
By taking two samples of the CCD signal and subtracting them, any noise source that is correlated between the two samples will be removed. Furthermore, a noise source that is not correlated, but is slowly varying between the two samples, will be reduced in magnitude. Noise introduced in the output stage of the CCD shown in Figure 1 consists primarily of kT/C noise from the charge-sensing node, and 1/f and white noise from the output amplifier. The kT/C noise from the reset switch's ON-resistance is sampled on the sense node, where it remains until the next pixel. It will be present during both the reference and data levels, so it is correlated within one pixel period, and will be removed by the CDS. The CDS will also attenuate the 1/f noise from the output amplifier because the frequency response of the CDS falls off with decreasing frequency. Low-frequency noise introduced prior to the CDS from power supplies and by temperature drifts will also be attenuated by the CDS.
A typical CCD signal has a dc offset of anywhere from 3 to 9 V or more. Dc offsets of this magnitude are generally incompatible with CMOS signal-processing ICs. In most scanner and high-end camera systems, the signal processors use 5-V supplies, while in camcorders and digital cameras the signal processors use supplies as low as 2.7 V. An on-chip input clamp accomplishes the necessary dc level shift, and only requires the addition of an external coupling capacitor.
The CCD's dark current causes a difference between the reference and data levels of the CCD signal, typically ranging from 10 to 80 mV. If left uncorrected, this offset will reduce system dynamic range, particularly after gain is applied. The signal-processing component applies analog offset adjustment to correct the average level of the offset, thereby retaining the dynamic range. With the majority of the offset removed in the analog domain, the digital image-processing circuitry can perform fine offset adjustment on a pixel-by-pixel basis to correct for dark-current variations.
A programmable-gain amplifier is needed to match the CCD signal's maximum amplitude with the full-scale voltage of the ADC. Different CCDs for scanner and digital camera applications can have peak amplitudes ranging from 100 mV up to 3 or 4 V. Most CMOS ADCs have full-scale voltage spans of 1 to 5 V. If the CCD signal only spans 25% of the ADC's full-scale range, then two bits of dynamic range will be lost. A gain stage will amplify the CCD signal to the appropriate amplitude and use the ADC's full dynamic range.
Lastly, the ADC converts the conditioned analog signal into a digital representation, to be externally processed by application-specific digital circuitry. The speed and resolution of the ADC is based on the pixel rate and resolution of the application. A CCD with a maximum dynamic range of 55 to 60 dB would require at least a 10-bit ADC, while one with a dynamic range of 65 to 70 dB would require at least a 12-bit ADC. Additional resolution may be needed to allow headroom for the digital image processing. For example, 6 dB of digital gain reduces the dynamic range of the ADC by one bit, because only half of the ADC's input voltage range can be used.
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