In the ASIC industry, there's much discussion about design complexity, validation cycle time, tools, and overall design methodology. There are concerns that today's electronic design automation (EDA) tools cannot keep pace with the requirements placed upon them by growing design complexity. This gap is expected to widen further with each advancement in semiconductor technology that reduces feature size and allows for larger, faster, and more complex designs. Intellectual Property (IP), the Virtual Socket Interface (VSI), large megacells, cores, and a myriad of rapid design methodologies will only continue to put more pressure on these design tools.
Product life cycles and time-to-market are placing increased pressure on users to get designs done quickly. Design verification must be accurate since errors can cause delays and increase costs, causing the design to totally miss the market window. What's needed is a three-way partnership between users, ASIC vendors, and the EDA tool vendors. But the question is whether the EDA community is in sync with the leading technologies of today.
With system-on-a-chip and ASIC designs approaching 1 million gates, it is clear that the industry is not at rest. IP, VSI, and reusable logic will allow users to quickly put more complex functions together. But whether there are sufficient tools and methodologies in place to ensure successful designs and design verification is questionable. How well the industry provides these solutions will determine the overall success and growth potential of not only EDA tool vendors, but also ASIC vendors and tool users.
Design Styles
Design styles directly influence design methodology and tools. Design styles for digital circuits can be fully synchronous, asynchronous, or a mix of both. In this article, fully synchronous is defined as requiring all direct action signals such as clocks, sets, and resets, to originate at the pads.
Some consider fully synchronous to include only a single master clock, but even in designs with a single master clock, glitches can occur in decoded set or reset signals feeding sequential gates due to timing differences. This can result in potential circuit malfunctions that could cause manufacturing yield losses or even nonfunctional silicon. These types of designs are considered semi-synchronous.
Asynchronous designs usually have multiple clocks running various sections of logic or signals that can arrive at random intervals that are common in communication circuits. Most companies can dictate the design styles, especially if the types of circuits they develop lend themselves to a particular style.
It has long been considered that analog designs are difficult and that developing a digital design simply meant defining logic functions and making sure timing requirements are met. This is no longer the case, since digital designs are beginning to take on more analog characteristics. It is becoming more important to have a closer link between Spice and validation processes, especially with designs that are not fully synchronous. As long as designers develop asynchronous circuits and design complexities continues to rise, verification accuracy will continue to be a major industry focus.
Power consumption also is becoming important, especially in battery-operated applications. This is accomplished by lowering the supply voltage in addition to disabling certain portions of logic during operation. Both methods of power conservation can cause side effects and require accurate timing verification. Shrinking process technologies also can reduce noise immunity since narrow glitches can be detected and passed on by other logic functions. Wire interconnect, once considered an insignificant part of the overall delay, is now significant. While this new technology has enabled designers to build larger, faster, and more complex designs, it also has compounded the problem of design verification and physical design.
As designs continue to push performance, increase in complexity, and the use of deep submicron technologies, several technical issues continue to arise. The capabilities of all EDA tools are being pushed to the limit, making design verification challenging. With standardization of the two IEEE HDL languages (Verilog and VHDL), it is crucial to address the growing concerns for accuracy and capability. Other timing standards such as Standard Delay Format (SDF), and a new proposed Delay Calculator Language (DCL), also will assist in meeting the challenges of design verification. With the added focus on these standards, EDA vendors can put emphasis on value-added enhancements and not language semantics or simulator behavior. To get a deeper appreciation of these accuracy concerns, a more in-depth analysis of such issues as pulse filtering, signal skew, interconnect, delay selection, accurate delay modeling, and memory modeling is needed.
Pulse Filtering
Most simulators, including those compliant with VITAL and Verilog, allow for two different pulse-filtering modes: inertial and transport. The inertial mode, better suited to older technologies, filters out all input transitions smaller than the gate propagation value. As geometries continue to shrink, the transport delay mode has become more important. All pulses, no matter how short, are allowed to propagate to the device output, and many simulators allow the propagated pulse to contain an "X" state to indicate ambiguity in the signal value. This is important because during this region of uncertainty, the actual amplitude and duration of the signal is unclear and, depending on the technology, can cause the devices to fail. These problems can result in either nonfunctional silicon or yield problems when these glitches drive direct-action signals on sequential elements such as clocks, resets, and sets.
Any time that another event is scheduled on a device output before an already scheduled event has a chance to mature, the second event is considered to be preemptive. When the second event is scheduled after the first event, it is a positive preemptive event; when it is scheduled prior to the first event, it is a negative preemptive event.
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