[Design Application]
Tips For Using High-Speed DACs In Communications Design
Selecting The Optimal DAC Means Knowing How To Interpret Converter Specifications And Their Effect On System Performance.
The burgeoning digital communications market has generated an unprecedented demand for a new generation of high-speed digital-to-analog converters (DACs). Many of these converters are being used in the transmit signal path to reconstruct the complex analog waveforms demanded by sophisticated digital modulation schemes. Advances in very-large-scale integration (VLSI) and digital-signal processing (DSP) technology now allow for more of the signal processing to be performed in the digital domain. There are many reasons behind the digital shift: higher spectral efficiency and capacity, improved quality, added services, software programmability, and lower power.
Synthesizing communication signals in the digital domain typically allows the characteristics of a signal to be precisely controlled, if not predicted. However, in the reconstruction process of a digitally synthesized signal, it's the DAC and its nonideal characteristics that often yields unpredictable results. In some cases, it's the performance of the DACs that actually determines whether a particular modulation scheme or system architecture can be implemented.
Unlike high-speed video DACs used to recreate images on high-resolution PC and workstation monitors, the performance of these converters are often analyzed in the frequency domain with secondary consideration to time domain and dc specifications. Selecting the optimum DAC for a given application requires an understanding of how to interpret various converter specifications and their effects on system performance. In addition, achieving the optimum performance while realizing other system objectives demands careful attention to various analog- and digital- interface issues (to be covered in Part II of this article).
Responding to the needs of these emerging markets, semiconductor vendors are releasing a new generation of CMOS and bipolar DACs that range from standard products of varying resolution, speed, and performance to more integrated products incorporating various DSP functions. These DSP functions may include digital interpolation filters, which reduce the complexity and cost of the required analog reconstruction filter, or complete application-specific digital modulators for quadrature or spread-spectrum modulation schemes.
Better Performance Much design effort has gone into improving the frequency-domain (ac) and static (dc) performance of these devices, while meeting other system objectives such as single-supply operation, lower power consumption, lower cost, and ease of digital integration. Several semiconductor vendors have elected to focus their effort on designing high-performance DACs using a digital CMOS process. In fact, today's CMOS DACs have overcome many of the deficiencies associated with their predecessors, video DACs, and now provide performance that's comparable, if not superior, to their bipolar or BiCMOS counterparts. As a result, system engineers are wise to keep informed about the latest trends and product releases that can affect how designers craft a next-generation system.
This renewed interest in high-speed DACs also has highlighted many shortcomings in the way these critical devices are traditionally described. As many engineers are learning through painful experience, selecting a DAC for any waveform- reconstruction application purely based on resolution, settling time, dc accuracy, and glitch impulse can often provide results far worse than anticipated.
Although certain observations can be made about the effects that the static (dc) and dynamic (time domain) specifications may have on a DAC's frequency (ac linearity) performance, the cumulative effect still remains impossible to predict, which is why simulation models do not currently exist. Because both static and dynamic nonlinearities will manifest themselves in the frequency domain, and contribute to a DAC's large- and small-signal distortion performance, a high-speed DAC should be primarily evaluated using specifications and characterization data pertaining to its frequency domain.
The frequency-domain performance of high-speed DACs has traditionally been characterized by analyzing the spectral output of reconstructed single-tone sine waves (Fig. 1). Single-tone sine-wave characterization of any analog or mixed-signal component allows for the easy identification of its various nonlinearities. Until recently, most of this analysis was performed using only full-scale (in other words, 0 dBFS) sine waves at a few selected update rates, presenting limited insight into a DAC's performance in a real-world communications application.
The spectral output of a DAC will contain both harmonic (including aliased harmonics) and nonharmonic spurious components that weren't part of the original digitally synthesized sine wave. Figure 1 represents a single measurement point in which the DAC's amplitude, output frequency, update rate, and operating conditions are all uniquely specified. Changing any of these conditions will often modify the nature of these spurious components. Consequently, multiple measurement points using different synthesized waveforms with varying DAC operating conditions must be taken, analyzed, and plotted to accurately ascertain a DAC's performance. All of this activity must be done while capturing any significant performance trends. To ease the selection process, the datasheets of more recently released converters will contain several pages of characterization curves.
Dynamic Range Spurious-free dynamic range (SFDR), perhaps the most-often-quoted DAC specification, defines the difference, in decibels, between the rms power of the fundamental and the largest spurious signal within a specified band. SFDR is usually specified over the full Nyquist region extending from dc to one-half the data-update rate (fCLOCK/2).
Typically, the worst spur is harmonically related and constitutes more than 80% of the total harmonic energy. Therefore, total harmonic distortion (THD) is rarely plotted over frequency because it's often only 1- to 3-dB worse than the SFDR performance. However, THD characterization curves plotting the three most significant distortion components can sometimes be helpful in determining which specific nonlinearity(ies) (such as second- or third-order distortion) limits a DAC's performance. Then, the effects of that nonlinearity can possibly be avoided via careful placement of the reconstructed signal.
SFDR also can be specified over a narrowband or window that purposely excludes the worst spur. The usefulness of this particular specification is relegated to those narrowband applications (for example, clock generation using direct digital synthesis) in which the DAC's full-scale output is operated over a limited spectral region, with the notion that the dominant "out-of-band" spurs can be filtered. In these applications, generating signals that are centered at either one-quarter or one-third the DAC's update rate will typically provide the worst-case performance due to the aliasing-back effect of the DAC's second or third harmonic. Thus, it may need to be avoided.
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