The concept of an audio delay line is simple. The voice or music to be delayed is analog-to-digital converted and fed into a shift register or any digital delay or storage medium. The delayed (or playback) digital signal is fed into a digital-to-analog converter (DAC), and the result is delayed audio.
The circuit shown in Figure 1 is very low in cost, but it may not look much like a DAC. It's a one-bit oversampled analog-to-digital converter (ADC) also known as a delta modulator. The resulting digital stream (when integrated by a simple RC circuit) is an approximation of the audio input. Because the approximation is continually compared against the reference audio, it's continually corrected to be as close as it can be to the original. It's never right, but always close. The higher the clock sample rate, the better the approximation.
The audio input is ac-coupled into the positive side of a comparator, with a dc offset of VCC/2. The output of the comparator (Point B) is integrated by RX, CX (typically 10 kΩ, and 0.01 µF) and fed back to the negative side of the comparator. The digital stream (at point B) reappears at point D delayed in time. Because point D has the same integration time constant as point B, the resulting waveform at the audio output is the same as point C. Figure 2 shows the waveforms described above.
The circuit, run at a clock rate of 100 kHz, will give high-quality voice reproduction. Higher clock rates will provide near-CD quality. The comparator can be any standard (fast) comparator, such as the LM311 or the LM339 (a bit slower, but very inexpensive). The D-flop is any HCMOS device, such as the 74HC74, or CD4013. And, the delay line can be any digital storage media. Users should try different integration time constants for different types of audio to determine which sound the best.
Note that the audio output comes out at a moderately high impedance (due to the integrator) and has some clock feedthrough. A simple two-pole low-pass filter on the output will generally be sufficient to remove any low-level clock leakage present.
can this be made with parts from a local store such as radio shack?
Anonymous -November 13, 2009
forget hysterisis, probably just raise the noise floor anyway. to take this circuit beyond just a concept you need a good 'ol S+H to smarten up the comp output, satisfying the setup time for the f/f and thus eliminating intermediate states (ie less noise)
steve -August 27, 2009
idea: use digital out to select up/down direction of 8 bit counter (clocked at higher rate) for multiplexed output
Dan the unautomated -August 05, 2009
A possibility for this circuit would be to introduce hysteresis around the comparator. The values would depend on the input impedance, try a 1M trimmer and 500k resistor in series (output to +ve input) as a starting point. the effect of this would be to reduce surious transitions and unstable states at the input of the flip flop, improving the noise floor.
Anonymous -August 05, 2009
original comments seem to be removed, the first RC (point B) must be connected after the flip flop otherwise the comparator may oscillate at high input Z. Good illustration of delta-sigma principle, and it works fine. for long delays a giant shift register can made from sram with a counter to generate successive addresses.
Anonymous -July 09, 2009
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