Today's Table of Contents: 1. Viewpoint Exclusive -- NoC: The Superhighways Of Tomorrow's SoCs 2. Support Blossoms For IBM-Chartered 90-nm Process 3. Structured ASIC Platform Gains Tool Support 4. Simulator Visualizes Communication Systems 5. Automated IP Validation In The Works 6. Happenings - 13th International Workshop on Logic and Synthesis (IWLS 2004) - International Workshop on UML for SoC Design (USOC 2004) - Design Automation Conference (DAC 2004)
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************ 1. Viewpoint -- Exclusive to EDA Alert ************ NoC: The Superhighways Of Tomorrow's SoCs
Alain Fanet, President and Chairman Arteris Inc., Paris, France
Like small cities that grow into large metropolises with only ad-hoc city planning, today's SoCs face a traffic crisis that threatens to create unprecedented gridlock. For cities, unmanaged development and poor traffic planning lead to long delays for drivers and public safety risks. For SoC designs, the analogous on-chip communication and traffic-management challenges can result in sub-optimal performance, under-utilized process manufacturing resources, and a significant loss in designer productivity.
SoC designers should carefully consider this analogy -- or even closer to home, the evolution of PCI Bus to PCI Express on boards -- as a model that will address a growing issue with on-chip communication on complex ICs. Although much progress has been made in connecting the discrete components that comprise SoCs (like processor-specific bus architectures and interface adapters), until now there hasn't been a way to take a chip-wide, architectural approach to creating a true network on chip (NoC). As chip complexity continues to increase, a more global approach is required to effectively transport and manage on-chip traffic, optimize wire efficiency, and allow designs to scale in size, complexity, and IP block usage.
With the ever-increasing amount of on-chip IP blocks, designers are finding that traditional interconnect approaches can't cope with on-chip traffic requirements. Minor evolutionary advances in on-chip interconnect techniques have evolved from traditional bus-based architectures, including tiered or multi-layered techniques. In IP-laden designs, a single bus -- or even multiple synchronous buses -- is impractical due to large wire loads and resistances, resulting in slow signal propagation. In addition, as process geometries scale from 130 nm to 90 nm and below, the physical capacitance of wires causes them to become slower, a challenge further compounded because signals must travel a longer distance in more densely designed chips.
A true NoC approach provides a variety of benefits to overcome current on-chip communication limitations: Complexity/performance ratio: NoC is the only way to connect the dozens to hundreds of functions on today's SoC without significant performance degradation, and to scale to the needs of future generations. Cost: NoC using packet-based approaches improves overall "wire efficiency," allowing more efficient use of on-chip resources dedicated to interconnect. This results in reduced silicon area compared to traditional interconnect approaches. Improved overall design productivity: Adoption of a standard NoC architecture speeds IP integration, facilitates IP sharing and reuse as well as rapid derivative design, and enables faster timing closure in the design process.
Such a solution must be scalable to handle large numbers of IP blocks that need to communicate via the networks; it must support existing IP-interconnect protocols such as AMBA, OCP-IP, and Core Connect; it must also be compatible with existing embedded software design practices; it must be "designer-friendly" in terms of integrating into existing high-level design flows; and it has to introduce limited real-estate costs.
We believe an NoC approach represents the key to unlocking on-chip gridlock. The industry should be pursuing a solution that utilizes well-known and proven concepts -- switch fabric technology; globally asynchronous, locally synchronous (GALS) implementation; and support for existing design standards and methodologies.
Alain Fanet is CEO, chairman, and one of three founders of Arteris, a Paris-based startup focused on network-on-chip solutions. Previously, Mr. Fanet was senior VP and general manager of the High-Speed Internetworking Business Unit (HSI) within Globespan, an ADSL semiconductor company, and was president, COO, and co-founder of T.sqware Inc., a network processor company. Fanet holds a Ph.D in computer sciences from Ecole nationale superieure des telecommunications (ENST), Paris.
To comment on this Viewpoint, go to Reader Comments at the foot of the Web page: EDA Alert ==> http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0BIY50Av
DAC Panel: C Synthesis - Raising the Level of Hardware Design
A panel of Mentor Graphics customers including STMicroelectronics, Alcatel, Nokia, Siemens, Ericsson and IP-Flex will share their new high-level synthesis methodologies and provide insight into designing compute-intensive applications, including wireless and satellite communications, and video/image processing. Following their short presentations, you will have an opportunity to chat with the panelists and Mentor executives.
Register for this panel today at: http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0BIY60Aw
******************************************************************* ******* 2. News ******* Support Blossoms For IBM-Chartered 90-nm Process
Cadence Design Systems, Magma Design Automation and Synopsys Inc. have all announced support for the 90-nm process common to Chartered Semiconductor Mfg. and IBM Corp. Cadence rolled out a qualified reference design flow that seamlessly integrates intellectual property developed by Artisan Components. The RTL-to-GDSII flow is based on Cadence's Encounter digital IC design platform and uses a wire-centric methodology to address key 90-nm design issues.
Magma is making available a preliminary 90-nm RTL-to-GDSII design enablement kit for the IBM-Chartered process. Included is a standard-cell library, Magma technology and setup files, and a reference design flow. The kit is for use with Magma's Blast Create, Blast Plan and Blast Fusion tools.
For its part, Synopsys validated its Galaxy design and Discovery verification platforms for the IBM-Chartered process. The flow uses Artisan's SAGE-X standard cell libraries and is verified from RTL to GDSII verification.
Cadence ==> http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0paF0At Magma ==> http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0BCfz0AD Synopsys ==> http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK05z30A1
******* 3. News ******* Structured ASIC Platform Gains Tool Support
An RTL-to-GDSII design flow for structured ASIC designs is the fruit of a collaboration between Magma Design Automation Inc. and Faraday Technology Corp. Magma's RTL-to-GDSII IC design flow has been adapted to support the creation of floorplans, physical synthesis, legalized placement, clock tree synthesis, and power routing for Faraday's Metal Programmable Cell Array (MPCA) structured ASIC platforms.
Magma and Faraday have already successfully implemented designs. In these initial designs, the fully automated flow was proven to exceed the design timing requirements by 10% with minimal run time.
Faraday Technology Corp. ==> http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0BIY70Ax Magma Design Automation ==> http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0BCfz0AD
******* 4. News ******* Simulator Visualizes Communication Systems
The 2004 version of Applied Wave Research's Visual System Simulator (VSS) for communication-system design couples a time-based simulation engine with a circuit simulation tool integrated in AWR's design environment. Within such an environment, system and circuit designers work together to perform interactive, top-down analysis of analog and digital communication systems.
VSS 2004 now supports Linux platforms. It also performs RF budget analysis, calculating the cascaded performance of RF links. By adding dedicated behavioral PLL simulation blocks, interactive investigation of the dynamics of frequency synthesizers and frequency and phase modulators is possible. Through simulations, users can establish practical PLL design guidelines. Ultimately, they can utilize the tool to determine the best loop bandwidth, phase noise, transient response, and phase margin for their PLLs.
Prices for perpetual licenses range from $12,000 to $24,000, depending on configuration. The product supports Windows NT4, 2000, XP, and Linux.
Applied Wave Research ==> http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK06LA0AV
******* 5. News ******* Automated IP Validation In The Works
On the heels of joining the Virtual Socket Interface Alliance (VSIA), Atrenta will partner with VSIA's Quality IP (QIP) development working group to implement and automate the QIP's rules, guidelines, and documentation in its SpyGlass predictive analyzer tool. Doing so will enable ASIC and SoC designers to perform in-depth structural analysis on Verilog and VHDL RTL descriptions. It will facilitate assessment of the IP's quality and ensure that it complies with best practice and IP reuse guidelines based on the QIP rules. With SpyGlass, IP providers will be able to quickly create QIP-compliant IP, and integrators can use the tool to quickly verify incoming IP for compliance.
13th International Workshop on Logic and Synthesis (IWLS 2004) Temecula Creek Inn, Temecula, Calif. June 2-4, 2004 http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0BH7c0A7
International Workshop on UML for SoC Design (USOC 2004) San Diego Convention Center, San Diego, Calif. June 6, 2004 For more information: E-mail General chairs Grant Martin (mailto:gmartin@cadence.com) and Wolfgang Mueller (mailto:wolfgang@acm.org)
41st Design Automation Conference San Diego Convention Center, San Diego, Calif. June 7-11, 2004 http://lists.planetee.com/cgi-bin3/DM/y/ef4z0DJhTw0BSK0paP0A4
Advertising/Sponsorship Opportunities: Bill Baumann mailto:bbaumann@penton.com
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