[Design View / Design Solution]
Control High-Frequency Effects When Distributing Power To DSPs
High clock rates and signaling speeds in today's DSPs introduce a new set of power-related problems that require careful decoupling.
High-speed DSP system designs are becoming increasingly complex due to the DSP's clock speed and potential issues related to signal integrity, power distribution, noise, and electromagnetic radiation.
For these reasons, designers need to understand the importance of the minimum current-return loops and other high-speed phenomena. They must also apply good high-speed design practices to reduce these effects before it's too late. And, future DSP architectures will include wider data buses with more simultaneous switching. This increase will lead to even more transients on DSP power-supply pins, making it critical for engineers to learn how to deal with such problems.
To combat the potential noise, one needs to understand possible sources and their consequences. Today's high-end DSPs have clocks running at 1 GHz, and they send signals through I/O pins at rates approaching 500 MHz.
Fast switching signals lead to considerable harmonics, and pc-board traces can act as antennas. Noise degrades audio, video, graphics, and communications performance. When radiated through traces, noise can hinder getting a system FCC certification or a CE mark.
Some sinister effects arising from fast clocking and switching aren't immediately obvious. When powering up a high-speed DSP to a known state, the voltage regulator must be able to supply an inrush current as large as 1.5 A. Too much inrush current can send a voltage regulator into thermal or overcurrent shutdown, so choose one accordingly.
Due to poor regulation, supply-voltage fluctuations can also lead to random logic failures. To inhibit droop on the output of linear regulators, you normally add a capacitor. A large value can supply plenty of current during fast switching. But be careful, because linear regulators can handle only a certain amount of capacitance before they go into oscillation and create noise.
Board traces from the regulator to the DSP have an inductance. Yet even with good decoupling capacitors, a charge needs time to reach the proper level. The DSP's switching can load down the voltage regulator, and the resulting voltage droop can again lead to random logic failures. Even worse, random failures are hard to isolate and debug because designers must guess which board section might be at fault.
BACK TO THE SOURCE Today's sophisticated systems have more potential sources of noise than ever. One particularly important source that involves crosstalk is often neglected. In high-speed systems, signal ground paths are determined by the frequency of operation. In fact, a signal trace's ground return path can vary widely based on frequency. For low-speed signals (typically below 10 MHz), signals exit from the source into the load and return to the source on the ground path with least resistance, meaning the shortest path.
Things get trickier with signals above 10 MHz. Here, the current returns on a ground path with the least inductance, which means the smallest loop area. The return on the ground plane follows a path underneath the signal trace, which generally isn't the most direct or shortest path. The return signal then spreads out with a current distribution (Fig. 1). So the return paths of adjacent signals can easily overlap, leading to crosstalk.
Several techniques help minimize crosstalk, including trace spacing. While many engineers feel that setting them one trace-width apart is adequate, it's better to double that spacing on high-speed DSP systems to reduce return-loop overlap. (For differential signals, such as those on Ethernet or USB, follow spacing guidelines that lead to the signal pair with the required matched impedance.)
Remember that doubling the space between signals reduces crosstalk by a factor of four. Second, provide shielding for critical signals, like clocks, by routing them on an inner layer between the power and ground planes. If this isn't possible, an image plane (ground plane) can be used on the layer immediately below those critical signals.
When reworking a board and adding a signal wire, designers need to add a ground wire in parallel with it. This supplies a high-speed current return path and makes for the smallest area in the current loop. Without this extra path, the return current's path might create large loops and pick up noise.
When combating crosstalk, remember that fast edges create more harmonic energy, and thus, interference. Energy from odd harmonics dominates a signal with a 50% duty cycle, often the case with clocks and other DSP signals. An effective way to reduce this harmonic content is by slowing the rise time (TR). Doing so moves the curve of noise amplitude toward lower frequencies, which better attenuates harmonic components (Fig. 2). One method for modifying rise times adds series-termination resistors on traces. But sometimes, rise or fall times can't be manipulated due to timing margins like setup/hold times.
Terminating lines also reduces transmission-line reflections and ringing. Determining if a trace acts as a transmission line is accomplished when the rise time is less than twice the propagation delay (TP) in the line (that is, when TR < 2TP). For an FR4 type of pc-board material, TP is on the order of 1 ns for a 6-in. trace, and TR for today's high-speed DSP signals is about 1 ns. Clearly, it's smart to keep traces as short as possible. If a trace must be long enough to act as a transmission line, the designers must use proper trace-termination techniques like series termination (a resistor in line with the output driver) or parallel termination (a resistor to ground at the load). In doing so, a resistor should be selected that matches the trace's pc-board characteristic impedance to minimize the reflections.
ANALOG AND DIGITAL PLLs Another area of concern for noise is phase-locked loops (PLLs), which DSPs integrate in growing numbers. In fact, some DSPs use both analog and digital versions (Fig. 3). The analog PLL, implemented with an analog filter, finds use in applications that require low jitter, like a USB port. But it takes more silicon to implement this type because analog filters typically need large capacitors. The digital PLL requires no capacitors, making it smaller and with lower leakage current, which is useful in applications that require fast wakeup time and low power, such as cell phones. Yet it's more sensitive to power-supply noise and input jitter.
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