Conventional wisdom has it that the consumer market will drive the next stage of growth in electronics. But designers should also be aware of investments in the military command, control, communications, computer, intelligence, surveillance, and reconnaissance (C4ISR) infrastructure. It isn't necessary to be a defense contractor to participate. It may not even be necessary to have military systems as a target application.
Case in point: Over the past two-and-a-half years, Honeywell Aerospace and Cypress Semiconductor engaged in a joint project to upgrade Honeywell's existing 350-nm radiation-hardened silicon-on-insulator (SOI) technology to the 150-nm generation, based on Cypress' experience with 180- and 130-nm bulk silicon. Synopsys joined the effort in the past year, adding its porting tools and design flow to the new process technology. The company also made its design centers available to ASIC engineers who are developing chips on the new process.
The effort is providing something different to each company. Honeywell, primarily a military contractor, gets accelerated development of a new rad-hard/rad-tolerant process technology for its defense customers. Cypress, essentially a merchant chipmaker, gains experience with SOI, which could potentially bring the one-transistor (1T) DRAM cell to scale below 100 nm (see "Scaling The 1T DRAM Cell," p. 52). Synopsys expands its customer base and attracts design center business.
NO STOVEPIPES IN THE SKY Results from the three-company project are being monitored by the U.S. Department of Defense (DoD) for its new generation of military satellites. The satellites will use advanced custom chips that can pre-process raw information literally "on-the-fly" in orbit before passing it on (Fig. 1). The DoD is relying on a number of initiatives to create an IP-centric C4ISR system. Such a system will overcome the "stove-piping" of information that led to lapses in anticipating and dealing with the attacks of September 11, 2001. (To be fair, a number of these initiatives were set in motion well before that date.)
In mil-speak, stove-piping refers to information traveling up and down in an organization with little horizontal sharing between organizations. One recent example is the communication gap this June between the FAA and the U.S. North American Air Defense Command. The plane bearing Kentucky Governor Ernie Fletcher to President Reagan's funeral may have been seconds away from being shot out of the sky because while the FAA knew the plane had an inoperative transponder, NORAD did not.
The underlying concept is a sort of shared military/intelligence community version of the Internet, the Global Information Grid (GIG) (see "The GIG Is Up: A Guide To Netcentric Warfare Programs," p. 52). The GIG's backbone would be a network of satellites communicating with each other, with aircraft, and with earthbound users. It would constitute something more than a packet-switching backbone. To speed the dissemination of information, these satellites would pre-process intelligence and tactical data in space (Fig. 2) (see "A Netcentric Warfare Bibliography," DRILL DEEPER 8579). Accomplishing this, though, will require large and complex custom chips manufactured on advanced-geometry processes.
That's where the Honeywell/Cypress/Synopsys SOI effort comes in. CMOS built on SOI (Fig. 3) is subject to far fewer radiation-induced error sources and failure modes than CMOS devices fabricated on bulk silicon (see "It's A Jungle Up There: Radiation Effects In CMOS Devices," p. 54). Other approaches to radiation hardening exist, such as adding protective circuitry and error-correction software. But where gate density and throughput are critical, SOI permits the use of simpler circuits without error correction. SOI also yields about a 30% power advantage over bulk silicon and between 20% and 30% better performance. Additional circuitry makes the part not only rad-tolerant, but also rad-hard, improving performance and density even further. Honeywell's rad-hard 350-nm experience demonstrates between one-and-a-half to two times higher density with SOI than with a comparable-generation bulk-silicon technology.
FUNDING AND TIMELINES Recognizing the advantages of SOI, the DoD established the Radiation Hardened Microelectronics Accelerated Technology Development Program in July 2001 to establish on-shore capability for 150-nm SOI. Honeywell is one of two contractors under this program.
Gary Kirchner, director of engineering at Honeywell's Defense & Space Electronic Systems Solid State Electronic Center, contrasts the then state-of-the-art 350-nm SOI process technology with what is under development: "Honeywell's 350-nm technology had an ASIC capability up to 1.5 million usable gates with five metal layers. It ran on a 6-in. line at our Plymouth, Minn. facility. The 150-nanometer technology that we're co-developing with Cypress is capable of 10 million usable gates, has six metal layers, and runs on 8-in. wafers at Cypress' Bloomington, Minn. fab. When we port it back to our Plymouth facility, we'll also be bringing up an 8-in. line."
As of July, Honeywell has "the capability to do the full front end of the line, that is, creating the transistors up to the contact," Kirchner says. "That is being followed by a phase-two upgrade so we can do the full back-end metal. By the end of 2004, Cypress will be in full production, and by the end of 2005 or early 2006, we'll have transferred the technology to our fab."
Because they don't possess extra circuit-level hardening, Cypress' rad-tolerant ICs will spec lower total-dose hardness capability than Honeywell's rad-hard parts. But, Kirchner explains, rad-tolerant and rad-hard will be design-rule compatible, and the models and electrical performance will be identical between the technology at Cypress and the technology once it's moved to Honeywell. The same designs will be able to run in either facility.
THANKS FOR THE MEMORIES Like Cypress, Honeywell is excited about 1T DRAM, and not just because of its smaller cell size. It also uses very low power and can efficiently refresh the entire memory array all at once, with relatively long periods between refresh.
However, Honeywell has also been working with Motorola on magnetoresistive random access memory (MRAM) as a totally rad-hard nonvolatile memory component. MRAM is unlike either flash or E-squared memories, which are sensitive to total ionizing radiation and need extra shielding and error correction. Honeywell will create the rad-hard transistor underlayers and place Motorola rad-hard MRAM bits on top.
Please refresh the page if you have trouble reading this text.
Search Electronic Design
Email Newsletter
Sponsored By:
Electronic Design UPDATE provides readers with late-breaking news, opinions from industry experts, and timely technology stories. It's a unique opportunity to get your product message in front of engineers, engineering managers, and corporate managers while they're reading about critical information online.
Reprints
