In addition to all of the standalone FPGAs, designers are embedding FPGA technology into structured ASIC solutions and using it to enhance the performance of functions such as CPUs. One example of the first case is a family of structured ASIC products from Leopard Logic (see "Configurable Logic Solutions Wed FPGA Flexibility With ASIC Efficiency," electronic design, Feb. 16, p. 38).
The Gladiator family combines RAM-based configurable logic blocks with mask-programmable logic and a collection of dedicated resources. The five initial devices in the family will offer from 1.6 million to 25.6 million system gates (about 200k to 2.3 million ASIC gates); up to 256 18- by 18-bit multipliers; up to 16 phase-locked and delay-locked loops; and up to 256 blocks of dual-port RAM (36 kbits/block). On the largest chip, the configurable logic consists of 256k logic cells of mask-programmable structures and 16k SRAM-based logic cells.
In CPU design, Stretch Inc. merged configurable logic right into the datapath of a Tensilica RISC processor core to create a family of accelerated CPU cores. By using the configurable logic in the core to directly assist instructions, key operations can be accelerated to improve time-critical algorithms (for more, see "Instruction-Set Extensions Let CPU Accelerate Key Operations," electronic design, May 10, p. 36).
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