[Leapfrog: First Look]
Multicore MCUs Propel Performance To New Heights
A trio of multicore microcontrollers expands computing-power and bandwidth boundaries.
Pushing the envelope? Get an extra shove by adding a few extra processor cores to that high-performance microcontroller (MCU). Just such an approach was taken by Broadcom, Freescale, and PMC-Sierra: Start with high-performance 64-bit processor cores and multiply their effectiveness with one to three additional cores.
Multiple-core solutions offer benefits that aren't possible with a faster, single-core solution. Interrupt handling can improve with a multiple-core solution because each processor can handle an interrupt. Interrupt processing will be faster with a faster processor, but it must complete the interrupt-handling routine before moving on to the next interrupt.
Also, an application for a multiprocessor environment will be more complex, but typically it can be used on any number of processors. Some MCU solutions, like Broadcom's BCM1480, support NUMA (non-uniform memory access).
Striking similarities exist among the three MCUs. Each has multiple 64-bit processor cores tied to a high-speed, internal interconnect. All sport quad Gigabit Ethernet interfaces, which isn't surprising given that one of the target application areas is communications.
PMC-Sierra's RM11200 incorporates a HyperChannel interface along with dual PCI Express interfaces. Freescale's MPC8641D has two independent high-speed serial interfaces in addition to standard interfaces like PCI Express and Serial RapidIO. Dual SDRAM memory controllers deliver data as fast as it can be extracted from the off-chip memory. Broadcom's BCM1480 stays with the tried and true 133-MHz, 64-bit PCI-X interface for off-chip peripherals—but it's no slouch when it comes to communication or expansion. In fact, its support for NUMA via HyperTransport links enables multicore, multichip solutions with up to 16 processor cores.
Beyond their many similarities, each chip possesses unique features and uses different techniques that provide low-latency, high-throughput data flow.
A COUPLE OF MIPS The 1.8-GHz RM11200 is built around a 16-port XBAR nonblocking, asynchronous switch with a low latency of just 3 ns (Fig. 1). The device only uses 11 of the ports, so expect new chips based around the same architecture.
Each port has a bandwidth of 192 Gbits/s, and aggregate throughput measures 1.5 Tbits/s. All transactions are pipelined. Of note is the asynchronous switch, which eliminates the global-clock skew problem found in high-speed, synchronous designs. It also simplifies the interfacing of each port while boosting performance. A processor-specific port handles cache coherency and supports a bandwidth of over 200 Gbits/s.
PMC-Sierra has put a lot of design time into the cache. Each processor has its own level 1 and level 2 cache protected by ECC. With PMC-Sierra's Direct Deposit technology, data from peripherals can be placed directly into a processor's cache.
The MIPS cores are the latest design with seven-stage superscalar pipelines and an 8k entry jump prediction table. EJTAG and trace support are standard, because off-chip in-circuit emulation (ICE) is totally impractical with a multicore design.
The RM11200 has an interesting mix of peripheral interfaces. It sports HyperTransport and dual PCI Express interfaces. HyperTransport opens the RM112000 to a multiprocessor environment, though the interface doesn't support NUMA-based memory sharing.
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