Engineers have always relied on hardware to speed up simulation. Initially, it was considered a luxury used only by elite verification teams. But with 90-nm processes soon to go mainstream and system-on-a-chip (SoC) gate counts closing in on 100 million, hardware-assisted verification is now a necessity. Certainly, those engineers trying to functionally verify a 50-Mgate design know that a software-only simulation of the full chip at 5 Hz or less is a losing proposition, especially given time-to-market pressures. So unless you've got several weeks or months for software simulation, today's ever-larger SoCs need hardware, whether it's to accelerate software simulations, emulation, or both. Moreover, leading-edge trends in verification, such as the use of transactions and assertions, are steadily creeping into the mix.
Broadly speaking, there are two approaches to hardware-assisted verification. One, targeted primarily at design teams, involves systems based on FPGAs. The other concerns systems based on custom processor architectures. These are larger systems aimed at verification engineers. Both have their places in the verification process, and both come with pros and cons.
According to Gartner Dataquest, the market for "design team acceleration and emulation" systems will grow rapidly over the next few years. Gartner's latest figures show that market, which primarily consists of FPGA-based systems, topping out at $119 million in 2008. The market for "verification team acceleration and emulation," comprising the larger, costlier custom-processor-based systems, will likely re-trench a bit in coming years. That's because, according to Gary Smith, Gartner's chief EDA analyst, "power users are pushing verification back down to the design team."
One study by Smith showed that verification, outside of typical test planning and regression testing, can waste as much as 25% of a verification team's resources. "That's because the verification team spends a lot of time chasing 'don't cares,'" says Smith. "The design team knows the difference between a 'don't care' and what really needs to be verified."
The rapid growth in complexity at the register-transfer level (RTL) is driving many design teams to rely on simulation acceleration. Another factor is the growing amount of embedded software content and the need to validate that software before engineering samples of the silicon are ready. Use of hardware acceleration and emulation can mean dramatic advances in hardware/software co-verification long before silicon is done (Fig. 1).
FPGA-based systems have the advantage of being relatively inexpensive compared with machines based on custom architectures. They're generally smaller and more readily deployed, and they can fit on desktops or at the side of a workbench. Hence, they tend to be aimed at design teams. Some vendors, such as EVE, claim speeds of 20 to 30 MHz.
FPGA-based systems also have limitations and drawbacks. The design being simulated must be mapped to the system's array of FPGAs. Anyone who has attempted this task manually knows that it's quite time-consuming and can ultimately frustrate designers.
Only two vendors in the hardware market, Cadence and Tharas Systems, currently use custom-processor architectures. Historically, such systems tend to have greater capacities than FPGA-based systems, though today's larger FPGAs are beginning to close that gap. Custom architectures generally offer slower runtimes than FPGA-based systems. But they're highly scalable in capacity and offer much faster and easier compilation.
"If you want to take the FPGA prototyping approach, it's going to affect your design, because you need to design up front for partitioning," says Ran Avinun, product marketing director for Cadence's Incisive verification platform. "If you don't partition up front, and most traditional ASIC developers won't want to do this, you get to the point where you have a database that is a combination of multiple RTL blocks and models and, as much as possible, you want to map this automatically to the hardware."
"We push people to look at their designs and understand up front what it's going to take to verify it," says Duaine Pryor, principal engineer and architect in Mentor Graphics' Emulation Division. "If you understand up front that verification will require booting an OS or running a second of real-time instructions, then you'll set up your verification methodology so that things will proceed smoothly into acceleration. And you'll get the maximum benefits out of acceleration."
Rather than manually mapping the design to the FPGAs, it's better to use commercial mapping software, such as Synplicity's Certify, which will perform automatic mapping. Certify includes automatic I/O-pin multiplexing so FPGA pins can be shared, circumventing the common problem of running out of I/Os. It also provides various mechanisms for debug-logic insertion.
Some emulation vendors offer proprietary mapping software that's specifically geared to their systems' architecture. EVE has spent a year developing an integrated compiler that's built to take advantage of its ZeBu-XL system architecture.
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