Single-chip transmitters proposed by some IC manufacturers have good electrical performance, but they're often plagued by some drawbacks. For instance, they're hard to find in small quantities. Also, they become obsolete too fast. And, they rarely have a second source.
For frequencies lower than 50 MHz, RF power of 10 mW, and a maximum frequency-shift-keying (FSK) data rate of 2 kbits/s, the circuit shown in the figure can be an attractive solution. The IC used is the 74VHC04 very high-speed CMOS HEX inverter, which is multisourced and available off-the-shelf. Furthermore, if the application leaves two unused inverters, the cost of the IC is zero!
The RF signal is produced by a Colpitts oscillator, in which the active element is a CMOS inverter (IC1a) and the inductor is replaced by a quartz crystal. The equivalent crystal inductance resonates with its load capacitance (CL) split in two serially connected capacitors: CL1 and CL2.
L1 and L2 behave as choke coils at 40.680 MHz. Hence, the load capacitors are:
CL1 = C3 + [(C2 × CDV1)/(C2 + CDV1)],
CL2 = C4 + [(C5 × CDV2)/(C5 + CDV2)]
Using the negative resistance concept, the oscillatory condition can be written as:
For best startup conditions, Equation 1 must be as negative as possible. One can show that an optimum occurs when CL1 = CL2 = 2CL. Consequently, the network connected at the input and output of IC1a is symmetrical. The frequency shift (?f) to be produced by the varicap diodes (DV1, DV2) is imposed by the condition of minimum modulation index:
mMIN = (Df/fmMAX) >= 0.5 (2)
This condition yields DfMIN = ±1 kHz, for a maximum data rate of 2 kbits/s in Manchester code.
To prevent forward conduction of DV1 and DV2, the minimum biasing is limited to 1 V by the R1-R2 divider network. Taking into account these constraints, and the startup conditions, we specified an AT cut quartz crystal in fundamental load resonance, with a load capacitance, CL = 8 pF.
With such a crystal and the capacitors' values shown in the figure, a load capacitance variation DCL = 1.6 pF is enough to reach: DfMIN = ±1 kHz.
The RF power amplifier is made with the CMOS inverter (IC1b) associated with an impedance matching network (L3 to L6, C7 to C10). Transforming the square-wave inverter's output voltage (VO) to an effective radiated power of 10 mW on a 50-W antenna involves two main operations:
1. Transformation of the fundamental term, 2(VDD/p), to a power of 10 mW on a 50-W antenna. This is done by calculating the optimum input resistance (RL) of the matching network. If RS is the inverter's output resistance, then the power generated at the fundamental frequency is:
Consequently, the optimum input resistance is:
Applying Equation 3 with RS(max) = 90 W yields: RL = 327 W. Taking into account components losses, the filter was finally: designed with: RL ~ 200 W.
2. Attenuation of the carrier's harmonics for complying with the European regulations (IETS 300 220-1). With a 40.680-MHz carrier, the magnitude of the first five harmonics is limited to: 36 dBm for H2, H3, and H4 and 54 dBm for H5.
If the filter's cutoff frequency is set just above the fundamental, then the number of poles (N@Hn) necessary for each harmonic (Hn) is given by:
N@Hn ~ (PHn PMAX@Hn)/Log(n) (4)
where: PHn = power of the nth harmonic prior to filtering, and PMAX@Hn = power authorized for the nth harmonic.
The number of poles (N) of the filter is the maximum number found when applying Equation 4 for each harmonic. We finally found that N = 8 poles. For testing purposes, the matching network has been partitioned in two sections:
1. A three-element 50-W to 200-W matching network, (C7, C8, L3).
2. A five-element 50-W to 50-W Chebyshev filter network (C9, C10, L4, L5, L6).
The spectrum measured at the output (VANT) shows that the CMOS transmitter can produce the maximum power allowed for the 40.680-MHz ISM band (10 mW) and comply with the European regulations. The current drain of the transmitter is IDD = 16.5 mA for a 5-V supply voltage.
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