Currently deployed WDM systems typically implement a dozen to several dozen channels, with each one capable of transferring data at rates of several hundred megabits per second. By tightening the channel spacing, more channels can be combined on a single fiber. Controlling the diode optical wavelength this way requires improved processing and device fabrication. Commercial systems capable of handling up to about 100 channels are now being deployed. With a channel-to-channel spacing of 50 GHz, these systems will typically transfer data at up to several hundreds of megabits per second for each channel.
Processing improvements permit designers to fabricate the laser diodes with much closer frequency spacing, letting systems pack even more channels on a single fiber. The current record, set late last year, spaces channels just 10 GHz apart. Researchers from Bell Labs demonstrated this ultra-dense WDM (UDWDM) system, which packs 1022 channels on a single fiber. Although the initial system only transmits data at rates of 37 Mbits/s per channel, the aggregate data-transfer rate rises to more than 37 Gbits/s (Fig. 2).
The emitters and detectors generally proved to be the limiting factor in this case. If the lasers operate at top speed, the co-integration of the large number of laser diodes used to generate the beams will create a lot of heat. To keep the power manageable, a lower speed was used in the demonstration.
As manufacturing techniques improve, diode power consumption per channel will decrease. So diodes can operate at higher frequencies and therefore deliver data rates high enough to let the system hit OC-48 rates (2.488 Gbits/s) per channel. This adds up to a total fiber capacity of several terabits per second. Think about the fact that 1 terabit/s is roughly equivalent to 20 million simultaneous, two-way telephone conversations, or the transfer of the text from over 300 years worth of daily newspapers. Imagine, then, that with this increased fiber capacity, bundles containing hundreds or thousands of fibers would be able to achieve pentabit-per-second data capacities. Scotty, start warming up that transporter.
Between the laser diodes and the host system, or the detectors and the host, lie the high-speed logic circuits. These circuits take the parallel digital data and create serial data streams (or deserialize the data). Advances in CMOS technology now let circuits operate at gigahertz speeds. To hit the 2.5- and 10-GHz marks, however, biCMOS and silicon-germanium (SiGe) technologies are starting to replace GaAs circuits. Until now, those circuits have been the workhorse technology for gigahertz performance. But GaAs and other III-V materials are the only technologies capable of operation faster than 10 GHz.
Manipulating The Data
It's one thing to move data across distances between computers or central exchanges. But before data is sent or after it's received, an entirely different set of challenges will have to be conquered. Data must be packetized and provided with headers that direct it to desired locations. In some cases, it also must be secured via various data-encryption schemes.
On the receiving end, or somewhere in its routing through the network, the packets also must be identified with header information. If the data isn't used to route the packet, it's stripped off and replaced with new header information for rerouting. All of this must happen at gigabit speeds, which are usually referred to as "wire speeds."
This process requires high-performance RISC processors, specialized memories like content-addressable memories (CAMs), and new static-memory approaches. The latest SRAM schemes, the zero-bus-turnaround/no-bus-latency approach, allow designers to build still faster hardware, just as the new quad-data-rate SRAMs will as systems using those devices start to emerge later this year.
Products like these won't be fast enough for future systems, though. A class of circuit has been created to solve some of the problems. Dubbed "network processors," these controller chips will typically sit at the edge of the enterprise and manage the flow of data.
Two major classes of chips are usually needed. One controls the switch fabric that ties the networks together, while the other processes the data packets to make sure they get to the desired destination. In both of these areas, no real standards exist. The data-transfer area, in contrast, leverages standards such as SONET to ensure data flows without any incompatibilities. For the moment, more than two dozen companies are vying to become market leaders in these areas. They've come up with significantly different architectures to try to provide solutions for the control and management of the packets.
To help bring about some order and hopefully move the market forward, many of the companies have cooperated to form two organizations: the Common Switch Interface (CSIX) Forum and the Common Programming Interface (CPIX) Forum. The CSIX industry consortium has been drafting a specification that defines the physical and message layers of the interconnections between network processors and the switching fabrics. The forum refers to this function as traffic management.
Such a standard would allow equipment manufacturers to accelerate the design of complex, "chassis-based" communications systems through the use of off-the-shelf components. These components provide the processing power and critical connectivity between the interconnect and the system. The first version of the CSIX specification will support up to 4096 ports, with communication at speeds of up to OC-192 (about 10 Gbits/s). (For more info about CSIX, check out www.csix.org.)
Trying to find some common ground between communications processors and other data and telecommunications entities, the CPIX forum plans to define a series of standardized application programming interfaces (APIs). The organization wants these interfaces to be used by designers to program and interact with communications processors. By developing them, it hopes to make it easier for system manufacturers to design new products, while letting them retain the ability to select the best communications processor to meet design requirements. (For more about CPIX, check out www.cpix.org.) In general, CPIX will focus on software standards, while CSIX will target hardware standards.
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