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[Technology Report]

Of Holodecks And Transporters: The Promise Of Unlimited Bandwidth


Looking beyond the imagery, huge data pipelines and distributed computers route and manipulate the data on Starship Internet.

Dave Bursky  |   ED Online ID #1022  |   January 10, 2000

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Standards are gaining even more importance as voice and data networks merge into one unified network. Interest has boomed around the use of the Internet Protocol (IP) as a transport scheme for moving voice and/or video packets. But unlike data transfers for still images and text, which can tolerate the late arrival of some information, voice or video packets must arrive in a predictable way. Otherwise, the sound or image will be choppy or unintelligible.

Until recently, high-performance RISC and CISC processors typically were at the heart of most pieces of network hardware. These 32- and 64-bit engines are software-driven, and thus limited in their ability to handle packets by the instruction throughput of the processor and the complexity of the task they must execute. The best of today's crop includes the UltraSPARC III from Sun Microsystems, which runs at 600 MHz. During demonstrations, the Alpha processor from Alpha Processor Inc. has clocked at 1 GHz. Various MIPS-based processors run at 400+ MHz, and x86-based CPUs from Intel Corp. and Advanced Micro Devices Inc. now hit 700 MHz and faster.

As a loose rule-of-thumb, David Sawyer, the president of Northchurch Communications, Andover, Mass., estimates that software-driven CPUs can provide about 1 Mbit/s of bandwidth for each MIPS of throughput. Unfortunately, no matter how fast CPUs are, that won't be enough. Bandwidth handling must increase by a factor of at least 1000 or more for systems to keep up with data demands.

Even desktop computers and other future devices will demand data rates of 1 Gbit/s and higher. Plus, more and more transfers involve audio and video information and will deal with multiple packet-transfer protocols. So quality-of-service (QoS) guarantees in Layers 3, 4, and 5 of the ISO standard will be essential to assure smooth and loss-free receipt of data.

Rather than cluster all of the horsepower in a single high-performance CPU, truly scalable end-to-end networks must distribute the intelligence across all of the elements in the network. Doing so makes each element network-aware. The switches, routers, and other pieces of network hardware must all be programmable and able to evaluate data flow to improve network efficiency. As long as they have these qualities, networks can be dynamically configured and hence respond faster to changing traffic patterns.

Custom silicon solutions have long been used to provide the higher performance that off-the-shelf CPUs can't deliver. The gestation period for an ASIC is 9 to 12 months, though. Much shorter turnaround times, or an intermediate solution, are needed to simplify system design and shorten time-to-market.

Consequently, programmable-logic devices, like field-programmable gate arrays (FPGAs), are taking on a more vital role in the network market. Their short configuration turnaround times and reprogrammability (for SRAM and flash-based devices) allow easy system updates for adding new features or fixing a bug.

Over the last few years, FPGAs were typically limited to support roles. After all, their densities weren't able to implement the complex circuitry needed for network control or data-packet manipulation. But the latest offerings from companies like Altera Corp. and Xilinx Inc. break that mold by giving designers circuits with capacities hitting 2 million gates. Still higher-capacity devices are on the drawing boards, as process feature sizes drop below 0.18 µm.

Specialized Hardware
As mentioned earlier, circuits such as network processors, edge processors, switch fabrics, and specialty memories like CAMs and pattern-processing chips can provide the hardware portion of the solution. Then, system designers can concentrate on the control software and features that they must include in the network hardware. Through the use of the standards fostered by the CSIX and CPIX forums, it will even be easier to develop that software.

An entire class of companies has evolved to meet the needs of such systems and make all of this a reality. The field does include a few long-established companies, such as IBM Corp., Intel Corp., and Texas Instruments Inc. But it's mostly composed of relatively new companies (typically five years or younger) that specifically solve network-bottleneck problems. These include Agere, C-Port, Entridia, Extreme Packet Devices, Innovative Engineering, Maker, MMC Networks, NeoCore, PowerX, Sitera, Silicon Spice, T.sqware, and Xaqti (now part of Vitesse Semiconductor). And that's not even all of them. You can get a more complete list by checking the forums' web sites.

Other companies also are joining in the exploitation of new CAM technologies. Kawasaki LSI, Lara Technology, Mosaid, Music Semiconductor, and NetLogic are culprits, along with the ASIC or intellectual-property providers that have CAM functions in their design libraries.

The bandwidth needed by the networks increases as the data moves further from the desktop. For instance, at the desktop, data typically demands interfaces to ISDN, xDSL, and 10-/100-Mbit Ethernet lines. Corporate-access point, which is the next level, generally finds those lower-speed lines aggregated to OC-3 and OC-12 (155 and 622 Mbits/s, respectively). The "edge" of the enterprise usually offers OC-12 and OC-48 interfaces (622 Mbits/s and 2.4 Gbits/s, respectively).

Interconnecting these enterprise organizations is the core backbone, which comprises both OC-48 and OC-192 (10-Gbit/s) SONET channels. As technology permits, the 10-Gbit/s interfaces will give way to 40-Gbit/s pathways and even faster solutions (Fig. 3).

At each of the above boundaries, designers face different challenges as they try to handle the ever-increasing quantity of data. Within the enterprise, for example, it's not enough to switch packets and prioritize them if you can't make any guarantees about delivering them. Systems must be able to identify specific critical traffic flows, such as data, video, voice, and lifeline, and then prioritize them in relation to all other flows. Under all conditions, the system must be able to guarantee that there will be availability of service (AoS) in the network for that traffic.




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