[Technology Report]
Dynamic Performance Is The Mantra For Analog And Mixed-Signal ICs
Third-generation communications applications are calling for improved dynamic range over a much wider bandwidth.
In a similar vein, designers are working to drive 14-bit transmit DACs to a 100-dB SFDR and a greater than 85-dB SNR over the full cellular bandwidth. At the same time, the operating frequency for these parts is being increased. Recent 14-bit DACs have demonstrated a 75-dB SFDR at 26 MHz and a 74-dB adjacent-channel power ratio (ACPR) sampling at 65 Msamples/s. The thrust is to propel that performance further, reaching greater than 85-dB SFDR and about 75-dB SNR over the 35-MHz bandwidth within a year. Designers also are striving to obtain 16-bit resolution for such parts. Of course, the major competitors have targeted 100-dB SFDR over the entire cellular bandwidth for 16-bit DACs within the next two years.
Others have in mind the creation of a perfect 14-bit solution by the end of this year. Analog Devices, for instance, plans to refurbish its 14-bit transmit DAC, says Stephen Lajeunesse, project marketing manager. To ADI, "perfect solution" means attaining theoretical SNR and SFDR specifications for the 14-bit transmit DACs. The manufacturer is refining its existing architecture by tweaking the current switches and sources for better linearity. It's also reducing the noise floor by cleaning up noise sources like substrate, clock jitter, thermal mismatch, and other such functions.
Climbing that same ladder are the intermediate frequencies generated. They're putting stress on the sampling and update rates of future 14-bit DACs. To simplify upconversion using a mixer or analog multiplier, higher-resolution transmit DACs will have to reconstruct output waveforms at frequencies beyond 400 MHz. The path will then be clear for the development of broadband multimode, multicarrier transmission in the next-generation cellular base stations.
Initially, the plan will be to generate an IF around 200 MHz, and then slowly extend that capability to 400 MHz within the next couple of years. Such progression will simplify the upconversion to the desired carrier frequency for transmission. Traditionally, the DACs have generated single-carrier TDMA signals at much lower frequencies, which require complex mixers and local oscillators or analog multipliers for upconversion.
Note the widening channel spacing in the newer standards. As it stretches, ACPR performance gets more attention to ensure minimal unwanted distortion in the adjacent channel bands. To remove the undesired signals from those bands, designers are incorporating on-chip digital-interpolation filters. Migration to 0.35-µm CMOS processes has made this integration feasible. In fact, Analog Devices demonstrates it in its latest 150-Msample/s, oversampling 14-bit transmit DAC (see "Wideband DAC Fosters Multicarrier, Multimode Transmission," Electronic Design, June 14, 1999, p. 37).
A Boost To In-Band Performance By suppressing the first set of images, the on-chip digital filter enhances the in-band performance of the multimode, multicarrier design. It also simplifies the use of the analog reconstruction filter that follows the digital-to-analog converter output. The challenge is to improve this on-board digital-interpolation filter to afford greater flexibility and higher output frequencies, while providing an ACPR of over 65 dB at IFs of 70 or 140 MHz. Consequently, data-converter designers are exploring higher levels of interpolation filters, going from current 2X to 4X interpolation. Integrated, higher-order filters must start appearing sometime before year's end.
Aside from dynamic performance, the new standards are demanding greater linearity over wideband operation. The architecture must be refined to achieve better ac performance at high sampling rates and wider cellular bandwidths. Developments indicate that the INL error is being cut to below 2 LSB, with efforts to achieve 1 LSB in the near future. But many designers feel that reaching 1-LSB INL in 14-bit or higher-resolution DACs is a bit of a stretch. A more reasonable specification is 2 LSB, which is possible with clever designs.
On the ADC front, suppliers are concentrating on raising the dynamic performance bar at higher and higher input frequencies and bandwidth. A 14-bit, 65-Msample/s ADC with an SFDR of 100 dB and an SNR of 75 dB has been introduced. Now, designers are contemplating pushing the sampling rate to over 300 Msamples/s, while trying to hit an input bandwidth above 1 GHz.
That's several times better than the input bandwidth of current ADCs. To realize that kind of bandwidth, designers are planning to incorporate broadband sample-and-hold circuits and amplifiers at the ADCs' input end. Meanwhile, at the digital end, they're exploring ways to combine such high-performance ADCs with digital downconverters in order to directly link them with follow-on baseband DSP processors.
To support faster outputs, these devices will opt for low-voltage differential signaling. As the converters begin exploiting the benefits of deep-submicron CMOS processes and operate at voltages below 2 V, insufficient signal headroom will be a major challenge. Differential input and output techniques will come to the rescue of these low-voltage, high-performance ADCs.
Please refresh the page if you have trouble reading this text.
Search Electronic Design
Email Newsletter
Sponsored By:
Electronic Design UPDATE provides readers with late-breaking news, opinions from industry experts, and timely technology stories. It's a unique opportunity to get your product message in front of engineers, engineering managers, and corporate managers while they're reading about critical information online.
Reprints
