Walt Jung's Update The May 13, 1993 Idea for Design, "Build Precise V/F Converter," is a reasonably simple voltage-frequency converter with good performance. Although it uses only two ICs and a few passive components, the circuit's simplicity belies some underlying keys to effectiveness. The original circuit is reprised with the original figure and the write-up above. In this "revisit" to the original, attention is focused solely on some differences that designers can implement to improve the circuit's performance.
The revised circuit is configured identically to the original for frequency scaling (see the figure). Similar caveats as to selection of low-TC timing components, R1-C1, apply in this case. These points may, in fact, be even more applicable due to better circuit stability. Overall dynamic range and linearity is a function of the V/F IC (U2), an AD654. Although the basic device is capable of output frequencies reaching 1 MHz, best linearity is achieved with frequencies of 100 kHz or less.
Likewise, although the timing current IT driving U2 can range up to 1 mA, avoiding the upper end of this range also helps linearity. Both of these linearity improvement points were used in the original circuit, which was capable of linearity errors of ±0.02% or less.
In the new circuit, these basic scaling parameter points are retained. With VIN set for 0.5-V full-scale, IT will be 500 µA, corresponding to a 50-kHz output. The circuit can handle an input overrange of 10% (VIN = 0.55 V). The scaling sensitivity can be expressed as either 100 Hz/mV with respect to VIN, or 100 Hz/mA with respect to IT.
In the original circuit, the V/F coversion follows VIN over a 3-decade range with low nonlinearity—that is, 5 mV to 0.5 V. With trimmer R3 used to null U1's offset, the range could be extended to about 4 decades. To get full use of this circuit, both high- (R2) and low-frequency (R3) trims were used.
A trend these days, however, is toward trim-free circuits. For the case at hand, taking into account full scale, this means providing some method of calibrating U1's voltage offset plus the scaling errors of R1, C1, and U2. Cumulatively, these add up to an adjustment of ±16% if calibration is addressed in classic fashion (such as in the original figure).
Another Technique An alternative method to accomplish this is by simply using stable, low-TC components for R1-C1, and provide an input multiplex point dedicated to calibration (not explicitly shown). The multiplexer first selects an accurate 0.5-V full-scale calibrating voltage. Then, with the V/F output frequency read by a microprocessor timer port, the full-scale calibrating data is stored (see the AD654 data sheet). With appropriate software, this provides full-scale calibration.
For U1 offset control, the best way is simply to use a zero-offset amplifier. This step fundamentally eliminates the need for low-scale calibration. An example of such a device is a chopper-stabilized op amp—for example, the AD8551. Chopper-stabilized op amps feature a typical offset of 1 µV or less and a drift of 0.02 µV/°C. Employed within the updated circuit, this combination of offset control essentially eliminates low-end errors due to U1's voltage offset.
However, there's a subtle point of operation regarding the minimum IT. The op amp internal to the AD654 has a typical bias current (IB) of 30 nA, seen at both pins 4 and 3. Left uncompensated, this current will cause a serious IT tracking error at low-scale inputs. For example, if VIN is 500 nV, IT will be 500 nA, which is 16 times IB. Without some means of current correction, IB would effectively reduce IT to 470 nA, thereby causing a 6%-of-reading frequency error.
The RA-RD network corrects this situation, by providing a compensating path for the nominal IB, flowing in matched resistors RC-RD. The IB flowing in RD then doesn't flow in the Q1 collector path, and the error is minimized. With resistors connected as shown, this enhances tracking accuracy at VIN levels below 100 µV. Although the IB compensation is only nominal, it's still worthwhile, because the cost is just two 1% resistors and C4. Moreover, it can reduce the effective current/frequency error with a 500-µV VIN to 10 nA/1 Hz.
Performance-wise, there's no substantial improvement in linearity over the previous version. There is, however, an enhanced dynamic range over which it's applicable. Another advantage is the elimination of hardware trimming if software calibration is used. There also will be U2 sample-to-sample variations in linearity.
The circuit can be operated at 500-kHz full scale by changing C1 to a 100-pF NP0 capacitor, with linearity error degrading on the order of 10 times or more. A stable source is recommended for power, such as a 5-V IC reference (a REF02 or similar).
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