[Design View / Design Solution]
Carefully Weigh The Tradeoffs Of Cell-Based Vs. Structured ASICs
When all is said and done, the structured ASIC’s shorter development cycle may well be the deciding factor for your design team.
Memory options in a structured ASIC were more constrained. Each master slice featured SRAM in fixed sizes and numbers. As a result, one of the team’s first decisions was whether it could construct the design efficiently with the SRAM configurations available in a structured ASIC platform. After reviewing the wide range of options available from leading structured ASIC vendors, the team decided this constraint wasn’t a limiting factor.
A second key consideration was the availability of expertise on the design team. Like many design teams across the industry in recent years, budget cuts have made significant impact on available design skills. While the team retained deep expertise in some areas of design, such as memory interfaces and IP integration, recent cutbacks diminished the team’s ability to address signal-integrity and testing issues. Moreover, few engineers had experience implementing high-speed serial interconnects. Finally, the team’s limited budget left no room to add resources to address these issues.
From a simple performance perspective, implementing the design in a 90-nm cell-based ASIC offered the most attractive option. Optimizing each functional block and retaining precise control over the entire IC layout let designers achieve approximately a 20% increase in performance over the same design implemented in a structured ASIC in the same 90-nm CMOS process. The 90-nm, cell-based approach also offered the optimal solution in terms of power dissipation. The designers estimated that the same chip designed in a 90-nm structured ASIC would dissipate approximately 70% more power than a comparable cell-based ASIC.
Development Cycle Time
The next key issue for the design team? Time-to-market goals. The initial product development schedule called for turning the chip design around in six months. Considering the rapidly changing market conditions and the flood of new competitors, the design team calculated that a longer design cycle would pose a major risk to the product’s success.
The ASIC design team calculated that increased exposure to signal- and power- integrity issues in a standard-cell approach would translate into a significantly longer development cycle—a crucial consideration given the project’s aggressive schedule. Resolving signal-integrity, power, and timing-convergence issues would likely require multiple respins of the design.
To minimize those issues, designers would need to devote more time up front for integrity checking, power-grid design, and clock-tree distribution. Layout turnaround times would likely be extended as the team grappled with multiple trials. Invariably, time-to-handoff would be difficult to predict. Furthermore, once the team reached that goal, it would still face the traditional eight-week or longer fabrication cycle. Overall, the team estimated that it would need 12 to 18 months to develop the chip in a cell-based ASIC.
Addressing those issues also would require designers with a solid background in concepts such as crosstalk, ground bounce, and power-supply noise. That requirement could pose a major challenge for a design team short on signal-integrity expertise and already operating on a limited budget.
In comparison, the team determined that it could reach the same goal using a structured ASIC in much less time and with significantly fewer risks. A structured ASIC shrinks the development cycle by reducing the number of mask steps in the design process. Unlike a standard-cell implementation where designers configure every layer of the device, a structured ASIC is embedded with preconfigured logic, memory, and I/O in its first few layers. Designers customize the device for their specific applications by configuring the final few metal layers.
The clock tree and power grid in the structured ASIC are predefined and precharacterized. Therefore, issues such as signal integrity, power integrity, and timing convergence are much more easily resolved because the physical synthesis tool can actively use the power and clock grids as an input to physical synthesis. In turn, that reduces the likelihood of multiple respins, common among many standard cell-based designs. It also offers a tighter link to back-end processes, which makes a single-pass handoff much more likely.
After extensive research, the designers determined that with a structured ASIC, they could go from netlist to engineering samples with their design in as little as two to three months. This significantly increases the ability to meet their tight development schedule. Figure 2 illustrates the typical time required by structured ASICs and cell-based ASICs for various stages in an IC design flow.
Development Costs
Development costs also were a major driver in the team’s decision-making process, particularly given the project’s constrained budget. The team estimated that developing a cell-based ASIC using a state-of-the-art process technology would likely require purchasing new tools for design analysis and physical verification. It also would likely take an investment into new system-level-awareness tools early in the design cycle and new signal-integrity analysis and functional-verification tools later on. Early estimates placed new tool expenses for a 90-nm cell-based ASIC design in the $300,000 range.
But the most imposing obstacle to implementing the design in a cell-based ASIC involved its large up-front nonrecurring-engineering (NRE) expense. Clearly, mask costs for a 90-nm, cell-based ASIC would run well into the millions of dollars.
In comparison, the cost structure of the structured ASIC looked extremely attractive. The architecture’s predefined clock structure helps simplify timing closure and minimize clock skew. Its embedded power grid would largely eliminate power-integrity issues and accelerate the place-and-route steps. And, its embedded design-for-test (DFT) structures minimize the need for time-consuming test insertion and functional/timing resimulation. Moreover, because the IC’s initial floorplan would be fixed, IP modeling and integration would require less effort and fewer engineering resources. The team estimated that new tool costs would run well under $100,000 to develop a structured ASIC.
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