[Design View / Design Solution]
Carefully Weigh The Tradeoffs Of Cell-Based Vs. Structured ASICs
When all is said and done, the structured ASIC’s shorter development cycle may well be the deciding factor for your design team.
The real savings, however, would come from reduced NRE costs. Instead of spending millions of dollars up front for developing a cell-based ASIC, the team calculated that it could develop the same design in a leading-edge, 90-nm structured ASIC for an NRE expense of less than $250,000 (see the table).
The primary drawback to using a structured ASIC would be higher unit costs. Given the structured ASIC’s lower gate density, designers estimated they would pay approximately twice as much per unit compared to a cell-based ASIC in high volume. However, because initial sales estimates called for shipment of only a few tens of thousands of units, volumes didn’t support the high NRE costs implicit in the standard-cell option at 90-nm node.
Designing the chip in a cell-based ASIC using a 130-nm process presented an interesting option. Though this design option didn’t offer the same density and performance benefits of a leading-edge 90-nm process, it did offer a mature, proven process technology that would lower risk and reduce the team’s break-even point in terms of cost. The proven 130-nm process offered significantly lower costs per gate and per I/O than a structured ASIC. That advantage was partially offset by higher SRAM costs, as SRAM is larger in the more mature 130-nm process technology.
The primary drawback to developing the IC in a 130-nm, cell-based ASIC was its high up-front costs and longer development cycle. While the 130-nm process offered lower up-front costs than a 90-nm cell-based ASIC, the half-million dollar NRE cost remained two to three times higher than that of a structured ASIC.
In addition, if product volumes fell short of expectations, the cell-based ASIC option would become less economical while the structured ASIC option would be profitable throughout a wider range of unit volumes. Finally, the team did note that if product volumes exceeded expectations, the NEC Electronics Instant Silicon Solution Platform (ISSP) structured-ASIC architecture (developed by NEC) offered a fast and simple migration path to the vendor’s cell-based ASIC technology and lower unit costs.
Tool Considerations
From a design-tool perspective, the standard-cell approach offered the design team maximum flexibility. The design team could use a wide range of tools, from multiple vendors, to develop its ASIC. But if team members opted to do so, they would invariably face some tool-integration issues and would have to accommodate the costs of tool integration and training within their budget. Another consideration was how many designers would have access to the tools. The high cost of cell-based ASIC design tools would limit the number of licenses that could be afforded.
In contrast, the use of a structured ASIC would require implementing predefined tools and a predefined flow. While this limited design flexibility, it also offered some attractive efficiencies. Traditional cell-based ASIC design is typically a highly iterative process. Problems created in synthesis are often only discovered downstream in timing analysis or physical design, because designers of cell-based ASICs use physical-synthesis tools that aren’t directly linked to the underlying silicon architecture. The tools don’t integrate knowledge of where power or clock routes are located. To maximize design flexibility, tool users must decide which wire-load model is best to apply for the design. Accordingly, calculations are largely based on estimates.
That fact makes physical design and place-and-route operations a highly iterative process in cell-based ASIC design. Timing closure often results in an unpredictable number of loops and is difficult to predict. With limited physical data, the tool can’t tightly correlate the end design with GDSII. Final place-and-route operations can become a long and time-consuming process.
Structured-ASIC design can eliminate much of this ambiguity by integrating the fixed aspects of the ASIC architecture into a physical-synthesis tool. As an example, through a partnership with tool vendor Synplicity, ISSP customers can use a jointly developed version of the vendor’s physical-synthesis tool optimized for the ISSP architecture, Amplify ISSP Pro.
By working off a detailed floorplan, the tool embeds knowledge of where the predefined power and clock routes in the ISSP architecture are located. It also integrates knowledge of the ISSP complex-multigate architecture into its calculations. The wire-load model is predefined with the slice selected by the designer. Also, because it already retains knowledge of the architecture’s design rules, such as its fixed ratio of flops, inverters, and multiplexers, a more highly optimized implementation can be created within a fixed device size.
Leveraging these predefined aspects of the structured ASIC architecture, the tool increases usage as well as lets the designer achieve a more predictable result. Typically, a physical-synthesis tool in a traditional cell-based design estimates about 40% of all routes in a design. Using an optimized tool with a partially predefined structured ASIC architecture, designers can come out of physical synthesis with approximately 70% of all routes fully known. That increased accuracy translates directly into faster timing closure, fewer design iterations, and ultimately, shorter time-to-tapeout (TAT). Figure 3 shows the ISSP structured-ASIC design flow, highlighting the position in the flow of Amplify ISSP Pro.
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