LEVERAGING STATISTICS
Enter statistical static timing analysis (SSTA). While traditional static timing analysis can supply a worst-case number for delays, it can't provide a sense of the distribution of performance versus yield (Fig. 1). Rather than simply determining best-and worst-case corners and attempting to arrive at a single value for delays, statistical timing analyzers propagate probability distributions. Among the inputs to SSTA tools are distributions of parameters, such as transistor channel lengths. The distribution of values represents how channel lengths can actually vary based on silicon data.
Because they consider probability distributions, SSTA tools accept information about variation and then simultaneously consider the different probabilities of single transistors being at different points in that variation space. "It can do an analysis. It gives you more information about the likelihood of meeting timing, essentially your parametric yield," says Bill Mullen, group director of R&D at Synopsys.
In addition to device variation, there's also interconnect variation. "SSTA tools can take information about the individual wires and relate that to the variation in the parameters for the metal at the different metal layers," says Mullen.
The goal of SSTA is to reduce the sensitivity to variability in global attributes, such as temperature and voltage. Analysis is performed on each type of variability to arrive at a probability density function, or PDF (Fig. 1, again) . This function represents a statistical look at how the device will operate across variations in the underlying parameter.
Ultimately, an SSTA tool combines these individual PDFs with those for all of the underlying parameters to achieve an overall distribution for a given node in the circuit (Fig. 2).
"Statistical timing is nothing but adding probability distributions and taking the maximum of them to find the new arrival point of a signal at a gate," says Mustafa Celik, CEO of Extreme Design Automation. "This is one way of doing SSTA. Another is instead of propagating distributions, you can propagate parametrized representations of the arrivals and delays."
SSTA: WHO AND WHY?
Now that we've defined SSTA, the next questions are who uses it today and why. There's no doubt that SSTA is a leading-edge technology. There are certainly designs at 90 nm that can benefit from the application of SSTA. But many industry experts feel that SSTA won't see widespread adoption until the 65-nm node is prevalent, or even until 45 nm gets out of R&D and into circulation.
"You need SSTA less at different silicon geometries," says Eric Filseth, VP of product marketing for digital IC design at Cadence. "At 130 nm, most designs don't vary enough to get huge value out of statistical methods. Our belief is that you'll probably need it at 45 nm. It's clear that people can do 65-nm chips without SSTA."
Regardless of the node at which SSTA sees broad adoption, usage models for it are beginning to take shape. One of the gating factors toward adoption is availability of process parameters. As a result, statistical methods have seen their earliest usage from integrated device manufacturers (IDMs) like IBM and Intel. In such cases, a single part might dominate an entire fab line. An Intel or IBM knows that it can sell any microprocessor it makes at some price. Therefore, it uses bin sorting of parts by speed, and SSTA is applied in an attempt to slide the distribution of speeds as much toward the high side as possible.
A fabless semiconductor house might also make use of SSTA, but it would do so for different reasons. Intel can bin-sort its Pentium chips, but a fabless house doesn't necessarily have that luxury. For many fabless houses, either the chip runs at rated speed with the proper amount of power consumption or it doesn't. In the latter case, it's deemed a failure and can't meet the application's needs. But the fabless house still wants to maximize the number of sellable chips per wafer.
"That's not necessarily the same as pushing the target frequency as fast as possible," says Blaze DFM's Andrew Kahng, "because you might have leakage power-limited yield loss. So statistical design still applies even to those who do not bin or bin crudely. For example, if a graphics company has a chip that can't be sold into the mobile space, maybe it can still be sold into the desktop space. So graphics-chip companies, as well as processor companies, have that flexibility.
Clearly, the IDMs have a distinct advantage in applying statistical methods to timing closure. "For example, an IDM has control of the process and private access to the foundry," says Kahng. "So the path that the statistics, statistical device models, model-to-silicon correlation studies, etc., must go through is at least internal."
For the fabless world, SSTA's adoption will depend on the availability of process data and tools with the ability to consume it.
"Most major foundries have long begun forming strategic partnerships that will have statistics traveling back and forth before too long," says Kahng. "One thing is that the tools need to be able to consume the statistics before there's any point to releasing them."
The transition to SSTA has begun, but it will most likely take the form of an evolution. Most see traditional STA and SSTA as complementary.
"People will continue using, wherever possible, deterministic techniques," says Ravij Maheshwary, senior director of marketing for signoff and power products in Synopsys' Implementation Group. While it doesn't currently offer statistical capabilities, Synopsys intends to evolve its existing timing closure tools—PrimeTime, PrimeTime SI, and Star-RCXT—in a statistical direction.
"There will be a transitional period where we'll use the deterministic STA and we'll use statistical analysis to handle the sensitivity checking," says Magma's Robert Jones. "So we can begin to eliminate some of that sensitivity and get to designs that are more reliable, passing silicon yield on every wafer run."
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