Standardization of the SystemVerilog hardware design and verification language as IEEE Std 1800-2005 was one of the most significant events of 2005 for IC development. Expect 2006 to be the year of wide SystemVerilog adoption, resulting in productivity improvements and more first-silicon successes.
SystemVerilog holds the key to many of the requirements of a modern verification system (see the figure). It adds advanced functional verification constructs, such as assertions, constrained-random data generation, and functional coverage, to the language so they can be used seamlessly with existing HDL-based environments. Another benefit of SystemVerilog is its schematic structure, which permits detection and generation mechanisms to work together.
In addition to greater use of SystemVerilog, the complexity of today's designs demands that SystemC modeling be integrated into RTL flows. This trend is currently driven primarily by the verification benefits inherent in SystemC—the ability to model and simulate something very quickly.
However, a new trend is emerging thanks to transaction-level modeling (TLM), which links design and verification much closer together (see "The Rise Of Transaction-Level Modeling" online at www.elecdesign.com, Drill Deeper 11775). TLM has been a major driver in SystemC's adoption, primarily for its verification benefits. Combining behavioral synthesis technology with SystemC and TLM will enable more companies to exploit abstraction for design as well as verification.
It's also crucial to recognize that design complexity has compelled new levels of specialization in project teams and increased interdependence between those specialists. Among them are systems engineers, software engineers, verification engineers, logic designers, mixed-signal designers, and product engineers responsible for post-silicon debug.
Too often, members of these various disciplines use poorly integrated manual verification methods. Moreover, the overall verification process isn't managed from a common plan with metrics that are relatable across those disciplines. Further adoption of verification methodologies will unify these disparate elements into a more holistic approach.
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