Mixed-signal IP presents its own set of challenges. Many fabless-semiconductor vendors are moving toward fast serial interconnects, such as from PCI to PCI Express, to take advantage of the latest standards. But getting the same throughput on a single serial line, which was possible on multiple parallel lines, requires use of a serializer/deserializer (SERDES) technology.
"SERDES technology means you're now embedding a mixed-signal piece into the IP," says Navraj Nandra, director of product marketing for mixed-signal IP at Synopsys. "This is typically circuitry that does clock and signal recovery with the data. We can develop nice mixed-signal IP to do this function, but generally it goes into a large digital chip. At this point, most SoC integrators are not knowledgeable of, or sensitive to, the analog issues. As a mixed-signal IP provider, we need to be cognizant of that and to provide deliverables, models, and views to make it easier for the integrator."
Mixed-signal IP of this nature often is provided as a hard macro in GDSII format, but that's not sufficient, says Nandra. "You need to provide timing files, Liberty files, and .lef models for floorplanning," says Nandra. "You need to show solid documentation to help the customer place mixed-signal IP in the right location on the chip, or else they'll pick up noise from digital gates that can impact the analog performance."
This creates special test issues for the IP provider. "To shoulder all of that as the mixed-signal IP unit inside Synopsys, we've had to go to compliance testing," says Nandra. "But that's not enough, either." Not knowing how a piece of mixed-signal IP will be used or in what context it will be integrated, it's incumbent on the IP provider to test it in worst-case conditions.
Synopsys builds such IP onto test chips with multiple noise structures that recreate a harsh, noisy environment. Those noise generators are then switched on and off, which drives nasty substrate currents into the analog portions of the IP and disturbs the power supply and the noise-sensitive nodes. Then the mixed-signal IP is recharacterized under these extreme conditions.
"In the case of, say, a PCI Express PHY, we look at things like jitter and bit-error rates to see if we still meet the performance we had in a quiet environment," says Nandra.
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