[Engineering Feature]
Back To Nature For Next-Gen Semis
While the fight to scale down rages on, semiconductor manufacturers look more to nature for new technologies.
3D trigate transistor: At the 2006 VLSI Symposium, Intel unveiled plans to develop a three-dimensional logic transistor called a FinFET (Fig. 4). With production anticipated by 2015, the devices promise improvements in standby current and reductions in leakage current that's plagued the industry for several years. Another promise expected from FinFETs is the potential scaling to the 10-to 15-nm range, assuming that manufacturing problems related to pitch (the space between transistors) can be overcome and 3D etching perfected.
PACKAGING TRENDS The semiconductor packaging industry faces its own set of challenges while transitioning to newer, more environmentally friendly materials and new standards introduced in the RoHS initiative. For instance, packaging companies must deal with increasing device complexity and keeping pricing down as material costs escalate. To combat these issues, the packaging industry has come up with some interesting new technologies:
Redistributive Chip Packaging (RCP): Flip-chip was an important packaging breakthrough that eliminated wire bonding and made ball-grid array (BGA) possible. Using flip-chip, a die is connected face-down to a board or substrate using the conductive bumps (balls) in a BGA.
Freescale recently introduced RCP technology, which takes flip-chip a step further by eliminating package substrates altogether. This increases interconnectivity in a way that can't be accomplished using today's organic substrates.
Organic substrates limit the thinness of the routing traces that connect wire bonds to solder-balls, and thus limit I/O density. RCP lets the bond fingers be pulled into the die, creating a smaller package with higher I/O density.
RCP packaging reduces the size of high-pitch packages by up to 50%. By eliminating the substrate and enabling large area batch processing, RCP lowers packaging costs. RCP allows for high-density pad array designs and provides significant design flexibility with improved noise, power distribution, and thermal characteristics.
Quad flat no-lead (QFN): QFNs are leadless, near-chip-scale packages (CSPs) that have become popular due to their compact size, reduced weight, and excellent thermal and electrical characteristics. With QFNs, die pads are exposed (Fig. 6), which brings about efficient heat dissipation and high power capability. Advanced Interconnect Technologies offers an ultra-thin QFN package with a 0.60-mm-thick package profile. The lower profile allows for board-space reduction, package efficiency in the zdirection, shorter electrical paths for increased power yield, and overall system weight reduction or a larger die thickness.
References 1. "International technology roadmap for semiconductors: executive summary," 2005 ITRS; PDF; hundreds of authors contributed to this document.
Drill Deeper at www.electronicdesign.com For more, see "New And Emerging Memory Technologies," Drill Deeper 13494, and "An On-Chip Parallelism Frenzy," Drill Deeper 13495.
Reprints
