Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Design View / Design Solution]
IP Networks And Emerging Video Apps Need Video Transcoding

Zhengting He, Cheng Peng  |   ED Online ID #13656  |   October 12, 2006


Prototype Implementation
Figure 2 illustrates a video-transcoding engine using MPEG-2 and WMV9 as the originating and target formats. Although the MPEG-2/WMV9 combination is expected to be very common, the programmability of DSPs makes it easy to handle virtually any combination of source/destination video formats.

The system's dataflow begins on the left side of the diagram, with the compressed MPEG-2 video file stored on hard disk, and ends with the flat-panel display through the Windows Media Player software. In this demonstration vehicle, the video is in NTSC standard (720 by 480 pixels) resolution and being transcoded at 30 frames/s.

The streaming receiver module running on DSP1 buffers the MPEG-2 stream and manages the input data for the MPEG-2 decoder module. The data-receiving operation is controlled by TI's Network Development Kit (NDK) library, which essentially is a TCP/IP stack. DSP2 also has an NDK-based HTTP server. It handles the streaming request sent by the Windows Media Player as well as transmits the ASF packets to it. The Windows Media Player then decodes the ASF packets and displays the video on screen.

One of the most interesting and challenging aspects of the dataflow is the interaction over the sRIO interface between the two DSPs. For each video frame transfer, this involves:

  • As soon as DSP1 completes sending the video frame, it continues to send what is known as a DOORBELL package in the sRIO protocol specification. The DOORBELL package generates a system interrupt on DSP2, which is notified that a frame is available and then starts WMV9 encoding. After the frame is encoded, DSP2 sends a DOORBELL package back to DSP1, which again triggers an interrupt to DSP1 to notify that DSP1 can continue to send over the next frame. In the actual implementation, a PING-PONG buffer scheme is deployed to parallelize the encoding/decoding and data-transfer operation. The sequence is followed in loop fashion until the demo is stopped.
  • The GUI block represents the control and monitoring functionality built into the system. The activity of the sRIO link and both Gigabit MAC (GMAC) links are displayed in real time. For the link transferring the MPEG-2 stream, the average data rate is 8 Mbits/s, which is typical for the standard resolution encoded at 30 fps. For the link transferring ASF packets, the average bit rate is 4 Mbits/s, which demonstrates that WMV9 is able to save about 50% of the bandwidth but still achieve similar video quality. For the sRIO link, the average bit rate is 124 Mbits/s.

Conclusion
The proliferation of video-encoding standards and the impact of bandwidth and latency limitations in the IP network have resulted in the necessity of video-transcoding technology.

Although the basic technology has been in place for quite some time, higher-quality video and eventually HDTV over the IP network requires a new video infrastructure architecture that includes sRIO and DSPs that interact with, and complement, the interface's transmission scheme. DSPs used in infrastructure applications typically need to have large on-chip memory to handle multiple channels simultaneously. In addition, they must give designers multiple I/O options, including GMAC and UTOPIA, as well as provide better internal dataflow. The C6455 DSP and the aforementioned demonstration software components are evidence that the challenge of video over IP can be met now and in the future.


<-- prev. page     1 2 [3]     next page -->

Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?



Reader Comments

Very good an

rkdurvas -November 02, 2009

POST YOUR COMMENTS HERE
Name:

Email:
Your Comments:

Enter the text from the image below


Please refresh the page if you have trouble reading this text.

Search Electronic Design
     
  
 
Web Seminar
Sponsored By:
Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
Speakers: 
Date: 07/01/08
Register: 

Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources