[Engineering Feature]
We Have Seen The Enemy, And The Enemy Is Heat
Today’s complex SoCs are prone to thermal issues that can cause field failures. Here’s how thermal analysis can help you ferret out those hotspots.
THE VIEW FROM TI For large systems houses, thermal analysis and management are taken extremely seriously. In the case of Texas Instruments, it's the subject of a company-wide initiative.
"We have what's called the Thermal Council here at TI," explains Darvin Edwards, manager of advanced package modeling and characterization and TI Fellow. "One of the intents of the Council is to educate each of the various business groups within TI as to the nature of thermal issues they'll face in their products." The Council meets to share lessons learned from various design projects.
Within TI, thermal analysis is a standard part of the design flow. Design teams run through analyses to determine whether there will be problems. "We have some rules of thumb," says Edwards. "For example, we check to see if there's going to be more than a 2X differential in temperature gradients across the die." If there are concerns, the product engineers are made aware of the hotspot issues and a power map may be generated for the die.
In the event of such issues, TI follows some best practices in efforts to ameliorate them. For one thing, the engineers will consider reducing the impact of hotspots by attaching the die directly to a high thermal-conductivity heat spreader, such as a copper plate. Then, if a die with hotspots happens to be a thinner die (say, 50 µm in thickness versus 400 µm), that would imply the need for chip/package co-design. A special case concerns packages with stacked die, in which hotspots on one die within the package can create hotspots on another.
Engineers at TI try not to cluster hotspots, if at all possible. Spreading them apart keeps each hotspot away from the "thermal footprint" of neighboring hotspots, keeping each of them cooler. This practice applies to pcboard design as well as to IC design.
If a given die has only one hotspot, the best place for that hotspot is in the center of the die. Conversely, the worst place is in a corner. Silicon itself is one of the best thermal conductors, so centering a hotspot in the die gives it the best possible position for heat spreading.
But when multiple hotspots exist, it's poor practice to cluster them in the center, which effectively creates one large hotspot. In such cases, it's best to distribute them relatively evenly over the die while still avoiding the corners and/or edges. So, each hotspot has a chance to dissipate its heat evenly through the medium of the substrate.
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