Multiple iterations on a selected plan ensure that the optimal solution space is located and that the resulting specification will provide the best starting point for the design. Then, the chip plan is moved to the design implementation team, communicated through Verilog headers, the bill of materials of the selected IP, constraints, and floorplan data. All of these factors can be exported for direct import into industry-standard formats to guide the plan through Cadence, Magma, Mentor, and Synopsys design flows.
New Use Model for Chip Estimation Chip-estimation tools currently automate the “feed-forward” from early chip planning into the EDA flow. But everyone knows that plans change. This is the primary reason why chip estimation is now being used alongside design-implementation tools.
What about using the estimators throughout implementation, checking back with a plan that has evolved based on implementation decisions or constraints? What about using them not as a replacement, but as a way to assess the overall impact of decisions about to be made, design walls to overcome, or just changes dictated by new needs for functionality based on market requirements?
Companies are starting to use chip-prediction systems to explore way-down-the-road options after design implementation has commenced. This is much faster and more resource-efficient than using a design implementation team and tools for exploration and estimation.
In an IC design flow, exploration with classic EDA tools can take hours, even days. Offloading this to the chip-estimation system slashes the time to minutes and can deliver significant time-to-market advantages for a project.
This use model requires the original plan—or a new plan—to be manually updated based on the changes made since the specification-to-implementation handoff occurred. But automatically extracting the data from EDA tools to “feed-back” into chip-planning systems is in development. This will make it much easier to keep chip plan and implementation design in sync and greatly simplify the use of chip estimation throughout the design implementation flow.
Enhancing existing EDA flows through the chip estimation allows logic and back-end designers to finally have insight into the impact (including cost) that potential changes will have on the packaged chip. Automating the interaction between implementation and estimation systems will enable more moles to be whacked during the critical stage of a design, when stakes are highest.
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