Eliminate Wire Bonding?
Many packaging experts consider TSV to be the next step in interconnect technology. In fact, TSV may very well displace wire bonding. Wire bonding is a mature technology easily implemented with existing equipment. However, it doesn't necessarily provide the shortest path lengths between IC die.
Also, wire bonding requires dies with bond pads located at edges. That will ultimately limit the number of connections to the length of the edges divided by the placement resolution of the wire-bonding machine, particularly when using surface-mounting technology (SMT). Wire-bonded stacked chips also need spacing between them, and the wires themselves take up space.
There's no question that wire bonding is an important technology tool, but it may face certain limitations in the future. Wire bonding requires vertical spacing between dies of tens of micrometers, and horizontal spacing of hundreds of micrometers are needed for the die-connecting wires. Moreover, it can be argued that wire bonds introduce potential reliability problems, though the record on this is far from certain.
Still, leading semiconductor IC companies continue to advance the widely used technology, which they believe costs less than TSV technology. Samsung recently used wire bonding to pack 16 NAND die into an MCP module that maxes out at a density of 16 Gbytes. "No one knows how far wire bonding will go," says Dongho Lee, principal engineer for the Interconnect Product and Technology Group at the Samsung Memory Division.
To solve the limitations of wire-bonding bumps, Tessera came up with a micro-contact chip-scale package (CSP) for reduced package pitch in high-density area-array CSP products. The package uses nickel/gold-plated copper bumps that allow for SMT assembling of the CSP to a board. The microcontact bump pad can be reduced to a diameter of only 200 µm, compared with 300 µm for a 0.5-mm pitch ball-grid array (BGA) package (Fig. 2).
Akita Elpida Memory Inc. says it has developed the world's densest MCP module, with 20 stacked die in a package 1.4 mm thick. To achieve such thinness, the company ground down individual dies to 30 nm thick and developed handling equipment for such thin die. Akita then used 40-µm low-loop wire bonding and devised a method to inject resin without disturbing the mechanical assembly.
More and more, flip-chip technology is being used instead of wire bonds. Flip-chip technology connects a die face down to a PCB or a substrate using BGA technology or other conductive bumps. This not only eliminates wire bonds, it also increases signal speeds and reduces overall size constraints.
Freescale Semiconductor took flip-chip technology one step further with its redistributed chip packaging (RCP) approach (Fig. 3). A form of PoP, it delivers a large degree of flexibility thanks to a standardized I/O pin layout. The top chip in an RCP approach can be any ASIC, such as memory, an applications processor, a Bluetooth module, or a camera module.
According to Freescale, RCP offers the best combination of desirable packaging attributes compared to SiP and conventional PoP methods. The company uses RCP technology in its mobile extreme convergence (MXC) platform, which features a single-core modem, a shared-memory subsystem, an RF power amplifier, and power-management functions. As a result, one can opt to put an entire GSM (Groupe Spécial Mobile) EDGE (Enhanced Data rates for GSM Evolution) or 3G radio into a package the size of a U.S. quarter coin.
Tessera's MicroPILR PoP technology could serve a broad array of chip and board applications for mobile consumer devices. It can enable package-to-package connections down to 100 µm and package-to-board links down to 0.3 mm (Fig. 4). Columns stand less than 180 µm high and can be tapered from diameters ranging from 40 to 375 µm. In comparison, solder-ball diameters range from 350 to 500 µm.
Samsung Electronics seeks to develop "true" 3D circuitry through its Fusion program. Described at last December's IEEE International Electron Devices Meeting (IEDM), the program's first device is an ultra-dense NAND flash memory that stacks 32-bit cells in two interconnected layers.
Initial cells are built on a bulk silicon wafer. Then, others are built into a thin SOI-like (silicon-on-insulator) single-crystal silicon layer grown on top of the back-end-of-the-line dielectric with a common source line through the two layers. The common source line solves a potential problem with a floating thin-body SOI structure that allows only one cell at a time to be erased. Samsung believes this SOI approach might be useful for logic circuits, too.
Also this year, STATS ChipPAC announced a stacked flipchip package for mobile telephone platforms. This 3D package combines baseband, memory, and analog functions in a single package-in-a-package (PiP) case.
Continued on page 3
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