Tsv Times Two
There are two main contending methods of implementing TSVs: conventional dry etching and laser drilling. It's also not clear whether or not it's more cost-effective to generate the TSVs at an IC wafer-fabrication facility or the IC packaging facility. Companies are now examining the suitability of laser systems for drilling a wide variety of substrates, such as ceramics, metal and rare-earth oxides, and polymeric materials of layered composition.
Generally, laser drilling of TSVs is viewed as more costly than conventional dry etching. Yet Jeffrey Albelo, director of the laser singulation group at Electro Scientific Industries, believes laserdrilling costs are lower than those incurred by dry reactive ion etching (DRIE) methods on a normalized cost per 1000 vias. He bases his findings on raw via-drill-rate data.
More companies now see TSVs as the solution to the looming IC interconnect crisis, which, according to the ITRS, could emerge within a couple of years. A semiconductor industry group already has put forth the first draft of a roadmap for TSV technology and hopes to publish it by the end of this year.
IBM announced it will begin sampling the first commercial devices that make use of TSV connections. By next year, the company also will have production quantities of a power amplifier that features up to 100 direct metal links to a power ground plane.
New Materials
IC chip makers have long known that scaling IC geometries downward can crunch the tiny aluminum and copper interconnect wires in IC designs, causing timing delays and other problems. The expected shift to copper interconnects in logic and DRAM circuits will increase unwanted resistivity levels.
Gold is expected to be used more widely for high-density 3D packaging. Kulicke & Soffa Industries recently developed Formax, a new gold wire for stacked and multi-tier applications, that offers consistent loop profiles, linearity, and stability. It's also capable of loop heights of less than 3 to 16 mils with wire spans up to 320 mils in diameter.
Carbon nanotubes (CNTs) may have a future as a material for 3D interconnects. CNTs potentially can carry more current per given area, with current density levels reaching 1 x 107 A/cm2. Fujitsu is developing CNTs for 32-nm designs and demonstrated CNT bundles in 32-nm via holes across 300-mm wafers at approximately 450°C, with resistance values as low as those for tungsten (Fig. 5). The company's researchers are trying to get as close as possible to matching the resistance of CMOS-compatible growth temperatures of 400°C.
Future Routes
How and when 3D packaging developments will evolve depends on a number of factors: How quickly will semiconductor IC manufacturers adopt novel packaging approaches? What cooling methods are needed to dissipate increasing heat levels? What are the compatible processing equipment and tools, and do they have the necessary alignment and accuracy levels?
Most IC experts believe that this may occur over several phases. In all likelihood, flash-memory wafer stacks with TSVs and conductive pastes will evolve. This will be followed by surface-to-surface bonding of ICs with surface bump pitches as small as 5 µm being used. Eventually, a system-on-silicon methodology will evolve in which memory, graphics, and other ICs are bonded face down to the microprocessor chip.
MEMS IC toolmakers are already developing tools suitable for the coming 3D era. Presently used for etching sidewalls and trenches with much larger line widths of hundreds of micrometers, these tools could be adapted for use with finer-line geometries of tens of micrometers typical for 45-nm and 32-nm processing systems.
A number of equipment providers, materials companies, and researchers have joined to create an international organization to address the technical and cost issues involved in creating TSV 3D chip interconnects. The Semiconductor 3D Equipment and Materials Consortium (EMC-3D) will develop processes for creating microvias between 5 and 30 µm on thinned 50- to 300-mm wafers, using both via-first and via-last techniques.
Equipment companies initiating the consortium include Alcatel, EV Group, Semitool, and XSiL. Among the materials companies are Rohm and Haas, Honeywell, Enthone, and AZ. Wafer service support comes from Isonics. Research partners include Fraunhofer IZM, SAIT (Samsung Advanced Institute of Technology), KAIST (Korea Advanced Institute of Science and Technology), and Texas A&M University.
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