[Engineering Feature]
Stanch The Bleeding Of Leakage Power At 65 nm
Even as leakage overwhelms their power budgets, IC design teams are finding ways to plug the holes that are costing them dearly at sub-micron nodes.
Attacking the problem So the design community and EDA vendors have turned their attention largely to the control of subthreshold leakage. Several low-power design methodologies are in use, and they all have their tradeoffs in terms of relative benefits and impacts (see the table).
One of the most common techniques being applied of late is multi-VT cell swapping. This technique involves use of libraries with two or more voltage thresholds. The idea is to provide synthesis options for simultaneous optimization of timing, area, and power. A library with a lower VT will leak more, but it will be faster than the high-VT library. Designers can opt to use slower, but less power-hungry, cells on noncritical paths.
"Multi-VT complicated things the least," says Sequence's Frenkil. "Use of multi-VT may mean a modestly longer timing closure period." However, Frenkil adds, the leakage gains to be had from multi-VT are not huge. "It usually cuts leakage in half," he says.
Reverse body biasing of transistors can also help with subthreshold leakage by essentially turning the transistor "more off." Gate leakage is directly proportional to the gate-to-substrate voltage, VGS. Increasing VGS reduces leakage, but it also lowers performance.
Opinions differ on the merits of reverse biasing. According to Frenkil, reverse body biasing is losing favor at advanced nodes. "It has less effect on leakage with scaling," Frenkil notes. But Apache's Dian Yang believes that back biasing can be combined with variable-threshold CMOS (VTCMOS) technology to dynamically alter VGS as necessary for leakage control in critical paths. For non-critical paths, a higher VGS can come into play full time for leakage reduction.
Apache's RedHawk-ALP tool for physical power integrity supports a number of techniques for leakage control, including VTCMOS back biasing and the insertion of power gating for memory IP.
Speaking of power gating, it's a technique that will come into play more at 65 and 45 nm. Power gating (or power shutoff, as some term it) entails the insertion of switches that shut off power to inactive functional blocks. There's good news and not-so-good news associated with power gating, however.
The good news is that it can profoundly reduce leakage power from one to three orders of magnitude. "For those seeking ultra-low leakage, they'll need one flavor or another of power gating," says Frenkil. The not-so-good news is that power gating comes with a host of complications to the design flow. In addition to having to figure out where to place power switches, you have to figure out how large or small to make them.
"The sizing of the switches is critical," says Frenkil. The larger the switches, the less they cost in terms of performance. But larger switches consume more area and degrade leakage reduction. Smaller switches save on area, performance suffers more, but there's more leakage reduction.
Power shutoff switches also can wreak havoc for chip floorplanning, says Frenkil. "If you are power-gating blocks on the chip, their power rails have to be separated from non-powergated domains. If it's more than just one or two, it's a real headache for floorplanning," he says.
Power-shutoff switches also can cause issues with rush currents and wakeup times. Upon closing of a power switch to a block, the rush current can be large enough to be damaging if not managed properly.
Finally, power-shutoff switches bring a number of issues related to functional verification. Are the control signals for all switches correct? Have floating outputs been rectified? Will there be issues with state retention for blocks that are turned off?
Focus on flows For all of the above reasons, it behooves designers to consider tool flows that account for these and other leakage-related factors. For example, Sequence's tools begin with exploration of the effects of power gating at RTL, enabling what-if analyses of the effects of gating various blocks. The flow moves on to automatic sizing and insertion of switches and then to a final voltage-drop analysis stage, including analysis of the effects of voltage drops on delays.
Sequence's flow, which includes Power Theatre, CoolTime, and CoolPower, takes a holistic approach to power from RTL to GDSII (Fig. 2). It's prudent for designers to consider the entire design flow when considering leakage, including the architectural level.
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