What’s so good about moving the sampling operation downstream? In a discrete-time delta-sigma ADC, there is, as in most ADCs, a switched-capacitor filter. Designing one requires the creation of fast settling circuits and an input buffer to eliminate sample glitches.
Also, switched-capacitor input filters set their poles and zeroes through capacitor ratios relative to the sampling clock frequency. Because capacitor thermal noise is inversely proportional to capacitance, the capacitors must be relatively large to obtain the best SNR.
In addition, to acquire an accurate representation of the input signal on a hold capacitor, the input stages must settle to a finite level dictated by the accuracy limits of the system. During acquisition, settling time depends on the systems’ exponential time constant and slew rate.
Why design discrete-time ADCs, then? Discrete-time input filter characteristics scale with clock frequency. Filter performance, therefore, always matches the sample clock rate. (One penalty for this, though, is that the higher the clock frequency, the more dynamic power is consumed.)
That link with the clock rate has made discrete-time attractive over the years. In a continuous-time design, the filter characteristic depends on conventional active-filter design rules. If the sample rate is changed to match input-signal bandwidth, the continuous-time filter must be retuned.
It becomes a real challenge to ensure that a wide range of sample rates can be supported from a single product platform. A further problem lies in achieving high linearity in highresolution implementations, because the loop filter requires a great deal of gain.
Continuous-time design was so difficult, it remained essentially a laboratory curiosity for decades. Yet in 2005, Xignal, a fabless German company with just 33 employees, said it could stabilize the clock using a novel inductive tank circuit.
Somewhat counterintuitively, Xignal also found that exploiting deep-submicron CMOS processes helped make highspeed delta-sigma modulators a reality. Not only do they help lower the cost of implementing complex multistage digital filters, they also support high clock rates, allowing wide inputsignal bandwidths. The rest of Xignal’s innovation included a high-speed, multibit third-order modulator and a tunable, high-gain, continuous-time loop filter stage.
In the long run, Xignal determined that the fabless model wasn’t going to be the route to riches in the world of ADCs. National acquired the company in January 2007 and put on a full-court press, applying its design and manufacturing prowess to productize Xignal’s innovation. The result was the ADC12EU050.
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