SYNCHRONOUS SWITCHED BUCK CONVERTER
A synchronous switched charger replaces the commutating diode with a FET to reduce loss (Fig. 4). This, of course, makes the control a bit more complex:

PWM duty cycle (D) = V_OUT/V_IN

Dissipation = (D × R_DS(ON)¹ ×I_BAT²) + ((1 – D) × R_DS(ON)² × I_BAT²) + ((R_S + R_Idc) × I_BAT²) + TL

TL (transition loss) depends on FET capacitance, drive efficiency, and switching frequency, and we’re again ignoring that in this analysis. So for the 0.8-A charge current example, two FETs with 0.02-O RDS(ON) and an inductor with 0.002-O dc resistance you get:

D = (3.8 × 2)/12 = 0.63
Dissipation = (0.63 × 0.02 × 0.64) + (0.37 × 0.02 × 0.64) + ((0.47 + 0.002) × 0.64) = 0.008 + 0.0047 + 0.3 = 0.31 W

In this topology, the main loss is in the inductor and shunt, and the overall efficiency is improved by almost 50% over the single-FET switch topology. If the charge current is 2 A, dissipation is ~2 W and efficiency is 89%. This efficiency improvement becomes essential when the charge current is high and if the input voltage is much higher than the output voltage.

For example, on a single-cell Li-ion charger with a 12-V dc power supply and a 2-A charge current, the duty cycle decreases to ~0.3 and the loss in the single FET topology is ~3.2 W, with the diode accounting for about 40% of the loss. The loss in the synchronous converter is about 2 W, a greater than 60% improvement.

SEPIC ARCHITECTURE
The single-ended primary inductor converter (SEPIC) is one topology that can be used in chargers when the power input voltage can be either above or below the battery voltage. This occurs often when an automotive 10- to 32-V supply is used to power the charger and the battery has multiple cells in series. SEPIC converters have two switching inductors (L1 and L2 in the diagram) and are a bit complex to analyze (Fig. 5). The output voltage is determined by:

V_OUT = V_IN × (D/(1 – D))

where D is the duty cycle of S1. And as you can see, at a duty cycle of 50%, V_OUT = V_IN. If D is less than 50%, V_OUT will be less than V_IN and if D is greater than 50%, V_OUT will be greater than V_IN.

The major efficiency factors in a SEPIC converter are the loss in the two inductors, loss in the SEPIC capacitor (C1), the on-resistance of the switch (usually an N-channel MOSFET), and the voltage drop across the diode. In addition, the loss due to ripple current in the input and output capacitors must be considered.

In general, a SEPIC converter is less efficient than a synchronous buck converter. But a synch FET can replace the output diode to reduce that loss factor. This makes the converter a bit more complex to control, though. Winding both inductors on the same magnetic core can reduce output ripple current as well as loss in the capacitor.

TRANSITION LOSSES
Transition loss occurs in all switchedmode power supplies and chargers, and it’s the energy lost due to switching the FETs. When switching frequency and charge current are low, transition loss may be small enough to ignore in the design analysis. But as these factors increase, it becomes significant and must be analyzed. Transition loss in a FET can be approximated by:

Loss (W) = 0.5 × V_DS × F_SW × I_DSPK × (tsw_ON + tsw_OFF) where:

F_SW = switching frequency (in Hz)
I_DSPK = Peak drain/source current in the FET
V_DS = voltage switched (drain/source)
tsw_ON = gate turn-on time
tsw_OFF = gate turn-off time

Transition loss grows with increased switching frequency. However, the size of the inductor and ripple reduction capacitors decrease as the frequency increases. In most chargers, physical size matters less, and you want to use the minimum switching frequency allowed by the choice of the inductor (usually 120 to 300 kHz).

But in chargers where the component size is a major design factor and FET capacitance can be minimized, designs using up to 1.2 MHz are common. Also note that the proper choice of FETs to minimize transition time is essential for low transition loss. However, as the current-handling capability of a FET increases, the capacitance and transition times also increase.

Therefore, a fast FET in an SO-8 package that can handle 10 A may have minimal transition loss. Still, a FET in a TO-220 package that can handle 50 A will be quite a bit slower, and transition losses may become a significant design factor. The transition loss calculation shown above assumes use of a FET gate driver with enough capacity. If this isn’t the case, tsw (on or off) will increase, increasing the loss. Gate-drive current requirements can be approximated by:

I_GATE = (C_ISS × V_GATE)/tsw

where:

C_ISS = FET input capacitance

V_GATE = gate voltage
tsw = on or off transition time

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