[Technology Report]
New Techniques Enhance Efficiency Across All Loads
Governments around the world are moving from voluntary to mandatory power-supply efficiency efforts. Challenges may lie ahead, but designers now have methods to cope with them.
The switching regulator efficiency across the load range is remarkably flat (Fig. 4). There are three modes of operation: PWM, pulse-frequency modulation (PFM), and shutdown. PWM is for loads of approximately 70 mA or higher. Lighter loads cause the device to automatically switch into PFM. That cuts the IC’s quiescent current to around 15 µA.
Each buck converter has a switching P-channel FET and a synchronous rectifying N-channel FET. During PWM operation, the converter operates as a voltage- mode controller with input-voltage feed-forward.
At very light loads, PFM mode means reduced switching frequency and supply current. The transition occurs if either the inductor current becomes discontinuous or if the peak P-channel switch current drops below a certain level, roughly 66 mA + VIN/160 O.
Here’s the interesting part. During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation. This allows more headroom for voltage drop during a load transient from light to heavy load.
Explicitly, the controller monitors the output voltage and controls the switching of the output FETs so that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the “high” PFM comparator threshold, the P-channel MOS power switch turns on.
It remains on until the output voltage exceeds the “high” PFM threshold or the peak current exceeds another preset level, this time roughly 66 mA + VIN/80 O. Once the P-channel MOS power switch is turned off, the N-channel MOS power switch turns on until the inductor current ramps to zero.
Now for the power savings. Once that N-channel MOS zero-current condition is detected, that switch is turned off. If the output voltage falls below the “high” PFM comparator threshold, the P-channel MOS switch is again turned on and the cycle repeats until the output reaches the desired level. Once the output reaches the “high” PFM threshold, the N-channel MOS switch is turned on briefly to ramp the inductor current to zero. Then, both output switches are turned off and the part enters an extremely low power mode.
The quiescent supply current during this “sleep” mode is less than 30 µA. When the output drops below the “low” PFM threshold, the cycle repeats to restore the output voltage to roughly 1.6% above the nominal PWM output voltage. If the load current increases during PFM mode, causing the output voltage to fall below the “low2” PFM threshold, the part transitions into fixed-frequency PWM mode.
ZILKER LABS Consider Zilker Labs’ ZL2004 and ZL2006 point-of-load (POL) regulators, introduced last January. Following on the company’s first product, the ZL2005, they combine a number of circuit techniques to maximize efficiency across the parts’ load ranges. The ZL2006 integrates 3-A MOSFET drivers that can support loads in excess of 40 A, and there’s no need for an external driver. The ZL2004 interfaces with external driver/MOSFET ICs and power-train modules.
The ZL2006 and ZL2004 use adaptive dead-time control, something included in the earlier ZL2005s. A proprietary technology dynamically adjusts the transition times related to turning on and off the synchronous MOSFETs.
Then there’s a new technique called “adaptive diode emulation.” As load current drops, typical synchronous stepdown converters will begin to sink current to maintain regulation. This removes energy from the output capacitor and reduces efficiency. The Zilker chips detect this transition point and prevent the lower MOSFET from turning on.
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