[Engineering Feature]
High Efficiency Challenges Power-Management Design
Designers face the formidable task of providing high-efficiency power management for processors that operate at 1 V and below, at 100 A or more, and at gigahertz frequencies.
Multiphase converters feature several important advantages. First, each cell delivers 1/n of the total output power, reducing the physical size and value of the inductors employed in each phase. Also, heat dissipation is distributed because power semiconductors in each phase only need to handle 1/n of the total power. This reduces any hotspot temperatures, increasing reliability and allowing higher total power capability.
Furthermore, equivalent frequency increases without incurring further switching losses, enabling the use of smaller equivalent inductances that shorten load transient duration. And, reduced ripple current in the output capacitor lowers the output ripple voltage and allows the use of smaller and less expensive output capacitors.
Multiphase converters also have some disadvantages that should be considered when choosing the number of phases. Primarily, there’s a need for more switches and output inductors below a certain power level than in a single-phase design, which leads to a higher system cost. Also, they require more complex control because of multiple converter cells. The possibility of uneven current sharing among the phases is possible. Finally, there’s added circuit layout complexity compared with a single-phase system.
As operating current requirements increase, there’s a need for more cell phases. An optimum design requires tradeoffs between the number of phases, current per phase, switching frequency, cost, size, and efficiency. Also, higher output current and lower voltage require tighter output-voltage regulation. Multiphase design decisions may employ any one of several available approaches.
One uses a pulse-width-modulation (PWM) controller IC with integrated MOSFET drivers. Yet heat and noise generated by the on-chip gate drivers affect controller performance. It’s impractical to cascade these types of chips to add more phases. Accurate current sharing is difficult with this configuration. And, three phases appear to be the limit. Another approach is to use separate controllers and separate gate drivers, with the PWM controller isolated from the heat and noise of the gate drivers. However, current sharing is more complex because the current-sense signal is routed to the controller. There are additional controller-to-driver delays because of the separated ICs as well.
Yet another approach is to use a controller with integrated gate drivers and built-in synchronization and current sharing. It would only permit an even number of phases, though. While it simplifies the design, it may result in unused or redundant silicon, pins, and external components. Most importantly, driver heat and noise generated on-chip can degrade controller performance.
So, existing topologies may not provide the freedom required in selecting the number of phases. The ideal solution is a scalable topology that makes it possible to easily add or remove any multiphase cell without sacrificing performance. This approach must be able to share current equally among the distributed phase cells. Such a technique minimizes parasitics and eases board layout.
CALL DRMOS FOR POWER EFFICIENCY One approach for configuring a reduced-size, scalable multiphase converter is to apply Intel’s Driver-MOSFET (DrMOS) specification (www.intel.com/design/pentium4/papers/drmos.htm) of November 2004. Fairchild introduced its first version in 2006, and it follows similar parts from Renesas and NXP, formerly Philips (Fig. 2).
One key advantage of using a multichip module for a DrMOS device is that the individual MOSFET’s performance characteristics can be optimized, whereas monolithic MOSFETs produce higher on-resistance (RDS(ON)). However, the component cost of a multichip module may be higher than a monolithic equivalent. Nonetheless, the designer should view the cost from a system viewpoint. That is, space is saved, potential noise problems are minimized, and fewer components reduce production time and cost.
Fairchild’s FDMF8700 is part of a suite of highly integrated “FET Plus Driver Multi-chip Modules” for use in high-current synchronous buck applications supporting Intel’s DrMOS Vcore dc-dc converter standard. The FDMF8700 is a fully integrated powerstage solution offered in a space-saving 8- by 8-mm micro-lead frame (MLP) package.
By replacing a 12-V driver IC and three N-channel MOSFETs, the FDMF8700 saves 50% board space compared to discrete component solutions. The layout and size of the switches and driver die are optimized to enable higher-frequency operation.
Unlike discrete solutions whose parasitic elements combined with board layout significantly reduce system efficiency, the FDMF8700 module both thermally and electrically minimizes parasitic effects and improves overall system efficiency. In operation, the high-side MOSFET is optimized for fast switching while the low-side device is optimized for low RDS(ON). This arrangement ideally accommodates the low-dutycycle switching requirements needed to convert the 12-V bus to supply the processor core with 1.0 to 1.4 V at up to 30 A.
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