Example 4: Power Switches This design illustrates several typical scenarios for power switches (Fig. 2). The design features three power domains. The first has a switched power net VDD1 that uses a header switch. The second contains a switched ground net GND2 with a footer switch. The third has an off-chip switched power net VDD3.
In general, a switched supply needs three bits of design information: (a) the “parent” supply, which is the input to the power switch; (b) the “child” supply, which is the output of the power switch; and (c) the enable signal. For externally switched supplies, (a) is not visible, but (b) and (c) are still required.
These three bits “hang” in different places in the two formats. Each bit of design information has a corresponding bit of library information. We need to know the supply input, supply output, and enable pin(s) of the power switch cells. Code list 7 and Code list 8 show the CPF and UPF, respectively, for the design. (Both skip the syntax already introduced.)
Section 1 is very similar for the two formats. CPF requires you to specify whether a net is power or ground. It also provides the opportunity to specify an external enable.
CPF clearly separates the three bits of information using different commands. Some of the information “hangs” directly from the domain object, and some is associated with a “rule” object. The create...rule commands define a rule, and the update... rule commands add further information to the rule. The parent supply net is associated with the rule in section 2, and the enable is associated with the rule in section 4.
The supplies aren’t associated using the rule, though. They are associated on the domain instead. The “internal” supply net is the one that’s connected to the standard power and ground pins of the standard cells. In some cases, this is an always-on supply. Sometimes it’s a locally switched supply or an externally switched supply.
For UPF, the example shows how two of the design’s bits of information, as well as some of the bits for the library data, are all captured together. Section 4 is very similar to the CPF section 4 with different terminology. UPF calls these nets “primary” supply nets, while CPF calls them “internal” supply nets.
Section 2, 4 shows the main UPF power switch command. The three “...port” options associate an instance pin name with a design net name. Therefore, “-output_ supply_port {VO VDD1}” means that the instance pin VO is the output or “child” supply and is connected to design net “VDD1.” The control port(s) and input supply port(s) are done the same way.
UPF provides simulation modeling for “on” states, “off ” states, “partial on” states, and “error” states. The simplest power switch has one control pin, and the switch is either on or off. However, a more complex switch may have multiple control pins. Each of the Boolean combinations of input values then can result in the switch being on, off, or partly on, or it may represent an illegal input pattern. In UPF, these are represented with named “states.”
Without going into more detail, the -on_state option here defines a state just named “on,” in which the input supply pin VI is connected to the output supply pin. The Boolean function of control pins under which this connection happens is “EN.” In terms of library pins, this command says VI drives onto VO when EN is high. In terms of design nets, this command says VDD drives onto VDD1 when en1 is high.
Section 3 defines the library cell for the power switches. There’s no specific syntax for this in UPF. Although the pin names of the library cell are implied by the pin names in the power switch command, there’s no opportunity to specify the name of the library cell. CPF requires you to specify whether the cell is a header or footer. It also provides for power switches that are “partly on,” with a stage 1 enable and stage 2 enable. However, the function is fixed, and the user doesn’t have the opportunity to specify Boolean expressions for the different states.
THE FUTURE The IEEE will complete and ratify P1801 over the next year. Also, Cadence will continue to promote CPF while the other major EDA vendors favor UPF. Still, a growing number of EDA vendors and design companies will likely use both. Something similar has happened with RTL design languages.
Almost all EDA vendors and design companies use both Verilog and VHDL. In some cases, a smaller company may be able to focus on a single RTL language. Most multinational companies that practice design reuse, however, wind up with designs that are partly in VHDL and partly in Verilog. Look for the same situation to occur with CPF and UPF. Thus, EDA vendors risk losing market share if they ignore one of the formats.
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