The direct path from PC to mass storage dramatically improves effective throughput. Cypress benchmarked the USB throughput of different consumer electronic devices in the market today. The benchmarking was done in a controlled environment (see the table). The names of these devices have been removed for confidentiality.
As the table shows, the West Bridge architecture significantly increases the effective throughput between PC and mass storage. This makes the West Bridge attractive for performance-critical systems.
Another benefit of adopting a West Bridge is to enhance design flexibility and enable expandability. Dual SDIO ports, for example, allow seamless peripheral connectivity such as Wi-Fi, Bluetooth, GPS, and many others. Designers can take advantage of dual SDIO ports to quickly spin off derivative products without a complete architectural redesign. For example, one can simply add a DVB-H module to an existing MP3 player design to create a PMP that supports mobile television.
A West Bridge also enables architectures to support the latest MLC NAND technology for cost-sensitive applications. MLC NAND cost is approximately 1/3 of SLC NAND, while MLC NAND devices are also available in much higher densities. Thus, in applications like PMPs and digital photo frames where high-capacity nonvolatile memory is required, the cost advantage of adopting MLC instead of SLC NAND is substantial.
The BOM can be further reduced when the West Bridge is used to facilitate processor booting. A typical embedded design has two nonvolatile flash memories: a high-density NAND for mass storage and a NOR or a smaller NAND for boot-code storage. A West Bridge can consolidate these by allowing the processor to boot directly from the NAND attached to the West Bridge (Fig. 4).
The processor boot code is migrated into the West Bridge NAND, hence eliminating the need for a separate flash. Note that the “P”-port is configured to support a NAND interface; thus, this migration is seamless and transparent to the processor. The West Bridge NAND is divided into two partitions: one for the processor boot code and another for mass storage. This usage model offers both BOM and board space reductions.
Apart from the BOM cost, utilizing a West Bridge can also streamline the manufacturing process of a product. As each model of consumer electronics is manufactured in millions of units’ quantity, manufacturing process efficiency becomes exceedingly important.
Time is money, and one of the most time-consuming tasks in the manufacturing flow is pre-programming of the NAND with processor boot code. Traditionally, these NAND devices are programmed with gang programmers, then mounted onto the product pc board. The shortcoming of this methodology is slow programming speed; it typically takes 20 minutes to program a single batch of NAND devices.
With a West Bridge architecture, programming can be done in-system using a USB host such as a PC (Fig. 5). Code can be transferred directly into the NAND via high-speed USB after the NAND is mounted onto the pc board. The sustained speed of this direct download is considerably higher and more reliable than using gang programmers.
A West Bridge architecture supports the latest mass storage and peripheral standards that complement embedded processors, bringing out best-in-class mass-storage performance while offering immense flexibility and expandability that greatly reduces product design time. Support for processor booting and manufacturing mode cuts down overall cost, giving West Bridge-enabled products a sizable competitive advantage. Examples of the West Bridge chip include Cypress Semiconductor’s Antioch (CYWB0124AB), in mass production since last year, and the Astoria (CYWB0224AB), which is expected to be available in the first half of 2008.
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