[Design View / Design Solution]
Designing For High Speed In Current-To-Voltage Conversion
As new communications systems reduce the number of RF up-conversions, design of the digital-to-analog stage becomes more challenging.
Figure 2’s transimpedance circuit is unstable without capacitor CF to roll off the noise gain. Without CF, the DAC’s output capacitance and the op amp’s input capacitance create a zero, and noise gain increases indefinitely at 6 dB per octave, causing instability. If RS is the paralleled resistances at the transimpedance-amplifier input and CS is total input capacitance (the sum of DAC output and transimpedance-amp input capacitances), the transimpedance amplifier’s noise gain is:
Choosing
guarantees stability, at the expense of bandwidth. The value that produces CF with 45 degrees of phase margin is:
This CF value starts to flatten noise gain before it intersects the op amp’s open-loop gain curve. To maintain stability, the slope difference between the two curves should be less than 12 dB/octave at the point of intersection.
A DESIGN EXAMPLE Let’s look at a high-bandwidth design. For an op amp such as Analog Devices’ ADA4899-1, typical differential RIN is 4k, and –3-dB bandwidth is 600 MHz at unity gain. A DAC like Analog Devices’ AD9755 has typical COUTDAC = 5 pF and ROUTDAC = 100k. DAC output capacitance and resistance are both code-dependent, but the typical values can be used to get a starting value for CF.
The DAC specifies a 300-Msample/s update rate and 61-dBc SFDR to Nyquist at 101.1-MHz output. If input data changes at least 2 ns before or after clock rising edges, the DAC shows a 63-dBc signal-to-noise ratio. SINAD is about 62 dB at 300 Msamples/s and 10 MHz, so the effective number of bits is 10 for those conditions.
The op amp can drive a 100-O load to over ±3 V. For a -1-V full-scale output voltage, use a 10-mA full-scale output current from the DAC and RF = 100 O. The op amp needs to sink the DAC’s full-scale current and the load current, so 50 O from the combination of RF and the voltage output load shouldn’t be a problem for a –1-V output swing.
Also, the op amp has a 120-MHz, –3-dB bandwidth for 1-V output across a 100-O load. Using Equation 3 with these component values, CF = 11.2 pF. This should be a surfacemount capacitor with low effective series inductance and resistance.
The transimpedance amplifier’s 3-dB output corner frequency is approximately:
For the example, this gives 69 MHz. But this CF value is only a starting point. Breadboarding the circuit and checking stability with real components is necessary to produce a working design. (More often than not, CF is determined empirically.)
The differential conversion offers more bandwidth. ROA-B in parallel with the DAC output capacitance and R1A-B in series with the op-amp inputs keep the noise gain reasonably flat for stability without extra compensation capacitors. Figure 3 shows the input and output capacitances and resistances between the DAC and op amp in the differential circuit.
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