For those seeking compliance with the RTL Design Style Guide of the Japanese STARC consortium of ASIC foundries, Aldec will show its ALINT 2008.06 STARC Lint design-rule checker. At any time during the verification flow from design entry to synthesis, Verilog and/or VHDL designs may be run through ALINT software, which compares Verilog and/or VHDL design languages against more than 280 pre-installed STARC design-rule guidelines (a pre-installed set of STARC rules).
This brings engineers instant feedback on structural, coding, and consistency problems early in the design verification cycle. Double-clicking on reported violations cross-probes directly to the line of Verilog and/or VHDL source code that’s creating the violation. ALINT is available today, and time-based license prices begin at $7500. Engineers may download a free 30-day evaluation license at www.aldec.com.
A newly launched startup, Nusym Technology, will have a demo suite at DAC to show off its “intelligent verification” technology, which uses design insight to enable rapid verification closure while leveraging existing methodology infrastructure. Nusym’s approach isn’t to treat designs in black-box fashion, but rather to report on real verification coverage, producing precise tests for hard-to-reach design structures while eliminating redundancy.
Celebrating its 20th anniversary, Tanner EDA will demonstrate version 13 of its tool suite and preview its 13.1 release. Tanner will also preview the Linux version of Tanner Tools with support for Red Hat Enterprise Linux V4 and V5, on the x86 and x86_64 platforms.
For analog/mixed-signal IC design-rule checking and netlist extraction, Tanner EDA’s HiPer Verify has been significantly enhanced with the introduction of Calibre- and Dracula-compatible hierarchical netlist extraction capability. HiPer Verify provides default property computations for built-in devices, or user code may be written to compute custom properties from a set of pin and auxiliary layers. Look for this feature with V13.1 in the fourth quarter. At DAC, there will also be demonstrations of a 64-bit Windows version of HiPer Verify.
Standards Evolving
At DAC, the Open Core Protocol-International Partnership (OCP-IP) will make available the latest revision of the OCP standard, OCP 2.2 Rev. A, which now includes consensus profiles. The organization will also provide a glimpse into the content for OCP 3.0.
The OCP-IP will also roll out its Debug Specification and whitepaper, as well as sponsor a Debug Workshop with ECSI. The specification details an approach to a standardized OCP-bus-compliant debug interface. The solution, an optional OCP port, implements a debug interface socket that can be added to all cores and IP blocks.
The specification supports a uniform method of on-chip system analysis and access to embedded information at the core, multicore, and system levels. The debug interface socket defines several layers of extended functionality to address the diverse and increasing debug needs for software, hardware, and mixed SoC prototyping. It’s intended to be compatible with other industry standards efforts that address debug and related on-chip issues.
Also on the OCP-IP’s plate is Part 1 of its NoC Benchmarking Specification. It details requirements and features for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Furthermore, it discusses ways to measure and benchmark reliability, fault tolerance, and testability of the on-chip communication fabric. There will be announcements at DAC regarding Part 2 of the NoC Specification.
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