After assembling the platform, Carbonized models allow analysis and exploration of the hardware architecture itself. They permit use of actual RTL to drive the architectural analysis and to use existing system modeling environments to validate assumptions regarding the architecture. Users can explore the performance parameters of the design implementation and verify that tradeoffs made using high-level system models were worthwhile.
Finally, the flow addresses firmware validation by enabling software debug before silicon is available. Firmware validation in the Carbon flow takes advantage of the accuracy of the Carbonized cycle-level models. It also makes for virtual platforms that are easily deployable to multiple design teams as well as to third-party software developers.
VIRTUAL PLATFORMS
By creating a virtual platform from hardware models, several software development issues are addressed. A virtual system gives designers much more control over the system compared to a potentially unstable first-pass silicon prototype. Thus, they operate within a far more deterministic scenario. Plus, they gain the ability to tinker with the platform at will, adding or subtracting functional blocks and/or changing their speeds to determine the effect on the architecture and system performance.
Virtual hardware offers good visibility in terms of memory, processor registers, and device states. When you synchronize the processors, you can synchronize everything at once. Virtualization also affords much more control over system execution. When debugging requires a global system stop, all processors stop simultaneously with no “skid” effect. When one processor is stepped through instructions, others can be made to sit and wait. Cores can be slowed or stopped entirely, communication latencies can be increased, and timing disturbances from breakpoints disappear.
One option for platform creation comes from CoWare in the form of what the company calls its ESL 2.0 toolset. With Co- Ware’s tools, SoC designers can debug and benchmark the platform- level performance of their IP and subsystem RTL at a cycle-accurate level of abstraction (Fig. 2).
CoWare claims a 30% to 50% cycle time reduction through the use of virtual platform technology. The technology accelerates the edit-compile-debug cycle. A virtual platform provides full visibility and controllability of the entire platform, including processor, buses, peripherals, and the environment, and is deterministic.
Yet another advantage of virtual platforms for co-design purposes is the removal of dependency on accessibility of the hardware. Just like a software package, the virtual platform is accessible—worldwide—in a matter of minutes, and thousands of units will have identical deterministic behavior.
Virtual platforms also help software developers sidestep rework that comes as a consequence of an evolving hardware specification. CoWare’s virtual platforms can be created with the same technology used by hardware architects and development teams. As a result, as changes are made, they can be immediately provided to the software developers.
BUILDING AN INFRASTRUCTURE
The virtual-platform route has its advantages, but there are also barriers to success. Building a virtual platform can be a laborious process that must be undertaken in parallel with the design process itself. Then there are the issues with interoperability of hardware models among various commercial flows.
Imperas, a startup in the virtual platform arena, made a splash earlier this year with a major technology donation that carries the promise of an open-source infrastructure for virtual platforms. Finding a lack of a broad debugging infrastructure, the company made three technology components freely available through its Open Virtual Platforms (OVP) Web site at www.ovpworld.org as well as at SourceForge.
The first component comprises C-language modeling application-programming interfaces (APIs) for processor, peripheral, and platform modeling that let designers build a platform-verification infrastructure as well as create behavioral and processor models. The second element is an open-source library of models written to the APIs. The models can be obtained as either pre-compiled object code or as source-code files. At the outset, the library comprised processor models of ARM, MIPS, and OpenRISC OR1K devices, with others to follow.
At last month’s 45th Design Automation Conference, Imperas announced a partnership with Tensilica that would allow fast functional, instruction-accurate models of Tensilica’s Xtensa and Diamond Standard processors to run on OVP-based virtual platforms. Specifically, wrapper files enabling integration of the Tensilica processor models are now available for free download at www.ovpworld.org. These models will run with Tensilica’s TurboXim fast functional simulator, which simulates at speeds 40 to 80 times faster than a traditional instruction-set simulator.
Last but not least of the three free components is a free OVP reference simulator that runs processor models at up to 500 MIPS. Known as OVPsim, the simulator comes with a GDB interface for the designer’s debugger of choice. OVPsim can be called from within other simulators through a C/C++/SystemC wrapper. It also can encapsulate existing instruction-set simulator (ISS) processor models (Fig. 3).
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