UWB In The 6- To 10-GHz Spectrum Presents Opportunities And Challenges

Designing above 6 gHz
Conventional wisdom in the semiconductor industry is that a single-chip CMOS wireless solution represents the lowestcost solution. It may not offer the best performance or lowest power, but many people believe it’s the least expensive, fundamentally because of Moore’s law in the CMOS world.

In an all-digital solution, a bulk CMOS single chip will almost always be the lowest cost among fabrication technologies. For wireless systems, that equation isn’t so straightforward.

For example, a paper by Zheng, et al1 showed that a singlechip system-on-a-chip (SoC) solution yields the lowest cost for simple RF solutions such as Bluetooth, but a SiP or module using a combination of IC technologies may better suit more complex RF systems (such as UWB) because of complicated yield issues. Several differences change the factors that go into deciding whether to use bulk CMOS, RF CMOS, CMOS + SiGe biCMOS, GaAs, or another process:

Operating frequency: dictated by specification
Bandwidth: dictated by specification
Absolute cost: from the market requirements
Power consumption: from market requirements
Adequate performance: meets specification and market expectation
Tradeoff of power and sensitivity versus cost: for example, in a cellular handset, a designer is willing to allow slightly more cost if it increases battery life or increases sensitivity (within limits)
Yield: important to a designer to minimize cost, but unimportant to the consumer
First-pass success: again, very important to a designer, but unimportant to a user
Architectural flexibility: ability to merge portions of wireless functions into an SoC or keep some portions outside, closer to an antenna, for example; another desirable architecture is a separate MAC and PHY, since WiMedia has defined a standard MAC-PHY interface, which allows manufacturers to mix PHY and MAC components from different suppliers
The consumer: this is a “don’t care,” as end consumers don’t care whether the chips inside the product are made from silicon, germanium, or potatoes; they just want the product to work and be reasonably priced

The reason that CMOS doesn’t automatically win in the wireless world is that Moore’s law doesn’t exactly apply to mixedsignal and RF circuits. To understand why, consider the 5-GHz WLAN transceiver shown in Figure 4.² Inductors and capacitors occupy much of the chip area, and a great deal of the IC isn’t used for any active or passive circuits at all. This is typical of almost all transceiver sections in wireless, and especially UWB. Furthermore, the area devoted to the inductors and capacitors doesn’t shrink linearly according to Moore’s law, so this empty space becomes very expensive at 90 nm and below.

To compound the problem, the signals are RF/analog and can be at quite low levels (10^-11 W at the LNA input). Smaller geometries create substantial noise and cross-coupling problems. These directly impact yield, first-pass success, and adequate performance. Thus, if a solution can be found that meets the other decision criteria and is the same or better in cost, there’s no inherent advantage to a single-die solution. In fact, a singledie solution may have some significant disadvantages if yields and performance are poor.

Specifically, at mid-2008 wafer prices, a strategy employing a CMOS process with SiGe implants in the RF section combined with a deep-submicron CMOS baseband processor and media access controller (MAC) actually is cheaper and performs better than an all-CMOS solution because of yield issues. Let’s examine the criteria above in light of this claim:

Operating frequency: Yields for frequencies above 6 GHz tend to be poor in bulk CMOS processes. That’s because getting the RF models for the circuits refined for high yields involves measurements of numerous test structures, especially for circuit geometries of 90 nm and below. Even with good test structure measurements, variation across process, voltage, and temperature for devices such as polysilicon capacitors in bulk CMOS can dramatically reduce yields in RF circuits. Metal-insulator-metal (MIM) capacitors in RF CMOS processes can have much better tolerances.
Bandwidth: The 528-MHz bandwidth requires ADCs capable of sampling a complex signal at a minimum of 528 Msamples/s at 4, 5, or 6 bits of resolution. This can be achieved using bulk CMOS.
Absolute cost: This is an important point. If we assume that the baseband + MAC has an area of 10 mm² in 90-nm CMOS, for example, and further assume an RF section that is 3 mm² in 0.13-µm SiGe, the RF might only shrink to 2.5 mm² at 90 nm. In this case, the packaged die for the CMOS with SiGe implants solution could be as much as $1.27 cheaper than the single-die CMOS.³ This solution is highly cost-effective because a process to add SiGe implants adds only a few steps to a conventional CMOS fabrication process, and yields are very high.
Power consumption: If a CMOS RF circuit is designed with one-generation-smaller geometry than a SiGe type, the SiGe circuit will consume 30% less power for the same performance.³
Adequate performance: By placing the LNA and other noise-sensitive structures on the same substrate as the digital circuitry, there’s significant risk that substrate noise will cause a loss of sensitivity. In one investigation, a singlechip CMOS WLAN SoC required 51 dB of substrate noise rejection, which is extremely difficult.⁴
Tradeoff of power and sensitivity versus cost: By decoupling the RF transceiver from the baseband + MAC, the designer can choose the most appropriate balance of power consumption, sensitivity, and cost independently.
Yield: According to Jazz Semiconductor, SiGe chips always have a higher yield than a CMOS RF die of the same size. This issue will be discussed later in more detail.
First-pass success: 95% of one CMOS + SiGe foundry’s customers sample to their end customers in 1.5 spins.
Architectural flexibility: The entire baseband + MAC could be assimilated into a 90-nm or even 65-nm SoC, leaving the CMOS + SiGe transceiver outside. Likewise, the CMOS + SiGe transceiver could be mounted in the same package as the baseband to create a standalone PHY. In each case, the performance of the solution would not be compromised by the partitioning. Integrating external passives into the SiP results in even greater savings.¹
The consumer: The consumer wins when a product is cheaper and works better.

The Right Path Forward
History shows that the challenges in developing bulk-CMOS RF circuits can eventually be overcome with clever design methodologies.

Performance and yield of CMOS UWB ICs will likely become acceptable over time, but it will require multiple re-spins of the design to converge to an acceptable solution. Mask sets for deep-submicron geometries are expensive and evaluation of test structures is time-consuming, so there’s a high risk for semiconductor companies that go directly to a bulk CMOS solution. It could take years and tens of millions of dollars to iteratively refine the CMOS solution to achieve acceptable performance and yield.

On the other hand, CMOS with SiGe implants is a much lower risk. Models are mature, but more importantly, yields in the initial spins of the design are much higher. As a result, the CMOS with SiGe implants, with its significantly higher yields above 6 GHz, skews the cost optimization dramatically away from a bulk CMOS solution, at least until bulk CMOS can achieve acceptable yields. In addition, probing wafers directly at these high RF frequencies is very difficult, so most vendors are forced to dice and package their parts before the RF can be tested. This ultimately multiplies the effect of poor yields, because packaging costs are incurred even on defective parts.

As an example, consider the case of a hypothetical chip that combines RF and digital functions. If the chip has to be packaged before test, then we can express the yield as:

If we assume a process that is CMOS with SiGe implants, then the estimated wafer cost premium over a bulk CMOS chip is about 20%, but the yields will be considerably higher for the CMOS + SiGe packaged parts. If we further assume that test and packaging for the parts will be approximately the same, then we can generate a comparison of the two strategies (see the table).

Using this spreadsheet, it can also be stated that if the CMOS + SiGe part has a yield of 70%, then the bulk CMOS chip must have yields in excess of 63.6% to achieve a lower cost. It takes several generations of bulk CMOS designs to achieve these kinds of yields in a mixed RF and digital part, but a CMOS + SiGe part can readily achieve these kinds of yields within two or three spins.

This implies that the fastest time-to-revenue is via a CMOS + SiGe solution, but that bulk CMOS can become cheaper if yields can be boosted to become within a few percent of the CMOS + SiGe solution. It should be noted, however, that the bulk CMOS solution may never demonstrate the low noise and excellent linearity and matching of the CMOS + SiGe solution.

The Best of Both Worlds
The best strategy for a company with limited resources would be to enter the market with a CMOS + SiGe solution that can yield rapid time-to-revenue while working in parallel on a bulk CMOS solution that leverages as much as possible from the SiGe effort. Once the CMOS architecture matures to the point where yields approaching those of the CMOS + SiGe solution, then chip developers can transition to a bulk CMOS design.

References

Li-Rong Zheng, Xinzhong Duo, Meigen Shen, Wim Michiels, and Hannu Tenhunen, “Cost and Performance Tradeoff Analysis in Radio and Mixed- Signal System-on-Package Design,” IEEE Transactions On Advanced Packaging, Vol. 27, No. 2, May 2004, pp. 364-375.
Ting-Ping Liu, Eric Westerwick, Nader Rohani, and Ran Yan, “5GHz CMOS Radio Transceiver Front-End Chipset,” www.bell-labs.com/org/physicalsciences/pubs/liu.pdf.
Xi Li, Evaluation Of Radio Frequency CMOS Integrated Circuit Technology For Wireless Local Area Network Applications, PhD Dissertation, University of Florida, 2003.
Mustafa Badaroglu, Stephane Donnay, et al, “Modeling and Experimental Verification of Substrate Noise Generation in a 220Kgates WLAN System-on- Chip with Multiple Supplies,” www.imec.be/esscirc/ESSCIRC2002/PDFs/C15.01.pdf.