[Design View / Design Solution]
Bulletproof Your System Timing With Programmable Clocks
By validating and then ensuring timing margin during development and production, programmable clocks help reduce system cost and optimize performance.
The bandwidth of the component PLL or different PLL bandwidths in two different components will track the reference clock jitter or spread-spectrum modulation differently. One way to think of this error, in the time domain, is as a delayed clock edge of a PLL that’s trying to follow changes in the system reference clock. Because the component’s internally multiplied clock may be used as the component’s input or output data strobe, this timing delay must be included in the data-transmission timing-error budget.
Based on Table 1, a system running at 250 MHz (1/4 ns) is reduced to 200 MHz (1/5 ns) due to timing errors. And before system-timing adjustments are made, even 250-MHz operation is marginal, depending on component and trace matching variations. Since the system is marginal, it may pass during prototyping or initial system validation, but fail during production.
PROGRAMMABLE CLOCKS Using the signal-integrity tuning features of an advanced programmable clock, the budgeted amount for several of these timing errors can be reduced. In addition, the confidence in sufficient timing margin can be increased by artificially introducing errors to validate the error modeling.
One example of a programmable clock generator that provides programmable optimization is the EPro clock from SpectraLinear. The various members of the EPro (Electrically Programmable) clock family incorporate from one to four low-power PLLs with up to 2048 nonvolatile control bits.
One of these clocks, the SL15300, allows fine-tuning of the output impedance (drive strength), output skew, operating frequency, and SS profile to minimize the timing errors as well as validate the amount needed for system timing margin. The PLLs can be programmed to consume less than 2 mA each. In addition, the program can be stored in internal nonvolatile memory or configured in real time through a twopin IIC port (Fig. 1). Table 2 summarizes the programmable capability of the SL15300.
The “After value” column in Table 1 shows that the programmable output impedance has been used to offset the load mismatch. Furthermore, the programmable skew minimizes the clock launch skew and offsets the systematic board trace mismatch. These parameters can’t be reduced to zero due to variations over process corners and the resolution of the programmable clock adjustment.
If further improvement is needed in the timing budget, the outputs can be programmed to be 180° out of phase, supporting the complementary HSTL (High Speed Transceiver Logic) format. In this case, most of the edge uncertainty due to noise is eliminated. That’s because the complementary traces are routed adjacent to each other and the complementary receiver rejects the induced common-mode noise.
The programmable features can also be used to determine system response to intentional timing errors. This debug tool is effective during development for measuring sensitivity of the system to various timing parameters.
In addition, the maximum frequency limit of the system can be determined by programming a specific part to have maximum timing-error deltas instead of the nominal values. This is accomplished by setting the skew, Tr/Tf, period, spread-spectrum magnitude, etc., to be equal to the maximum value allowed by the datasheet specification. Then the operating frequency can be incrementally programmed higher to the point of failure.
The last successful frequency is the maximum system frequency except for any production variation in the XMTR and RCVR devices. Production variations in the XMTR and RCVR timing can also be factored in by measuring the propagation and setup timing performance of those specific devices and using the difference between the measured and specified values to derate the measured maximum frequency.
Running a particular board at the highest operating frequency also allows various timing sensitivities to be examined. For example, if the maximum operating frequency is measured to be 222 MHz, then the spread-spectrum modulation amplitude is doubled and the new maximum frequency is found to be 217 MHz. Then we know that doubling the spread amplitude resulted in an additional 100 ps of tracking error (= 1/217 MHz – 1/222 MHz).
For the above example, the XMTR and RCVR timing parameters can’t be artificially increased to their worstcase values. Therefore, the difference between their measured values and worst-case specifications can be manually added to the minimum clock period to ensure the system will accommodate the process variations of future shipments. For additional safety margin, the timing component can be programmed in real time during production test to run at a frequency higher than nominal. This ensures that each system has adequate timing margin and will have no timing issues in the field.
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