The output frequency or frequencies of devices with high stability-holdover would only drift in response to environmental stimuli (primarily temperature and/or supply voltage variations) to the extent that the local reference drifted. For systems that must adhere to the holdover requirements predefined by some standard, it would be a simple matter of providing a local reference source whose stability meets the holdover stability defined in the appropriate standard.
So if the design required SONETlevel stability in holdover, the use of an oscillator that supports SONETlevel stability would provide what was required. If the clock signal were to drift in holdover, the result will eventually manifest as a FIFO error of some kind (overflow or empty) that would result in blank or skipped frames. Holdover can be initiated as directed by controller/processor elements in a system. Or, in many cases, devices with holdover also provide a monitoring function that will automatically switch into holdover mode when the reference input goes quiet. The output frequency or frequencies of devices featuring high stability holdover will only drift in response to environmental stimuli (temperature and/or supply voltage variations primarily) to the extent that this local reference drifts.
For systems that must adhere to the holdover requirements pre-defined by some standard, it is a simple matter of providing a local reference source whose stability meets the holdover stability defined in the appropriate standard. If you need SONET-level stability in holdover, use an oscillator that supports SONET-level stability. If clock signal drifts in holdover, the result will eventually be a FIFO error of some kind (overflow or empty) that results in blank or skipped frames.
Product Q&A
Analog Devices’ Clock Generators Simplify System Design And Reduce Clocking Component CountAnalog Devices’ AD9549 dual-input network clock generator provides networking and data communications systems designers with a new standard of performance to maximize network uptime and increase system stability and reliability. Using a new architecture based on ADI’s proprietary DDS (direct digital synthesis) technology, the AD9549 enables a more stable holdover, allowing designers additional time to restore the clock reference in the event of a failure. If an input reference clock fails, the clock generator IC continues to “hold” the output frequency until the reference failure is recovered. With the AD9549, there is no time limit to holdover—the output will be maintained until the system is powered down or a new reference is provided. Compared to competitive solutions, this holdover functionality improves stability by as much as two orders of magnitude (~0.37 ppm vs. ~30 ppm), resulting in significantly increased system uptime. The AD9549 dual-input network clock generator reduces jitter to 600 fs (femtoseconds), 25% better than competing devices. The AD9549 has a programmable digital loop filter capable of bandwidths down to 1 Hz and below.
The AD9520 and AD9522 multi-output clock generators include a 512-byte embedded EEPROM memory block, affording system engineers a programmable clock solution that can serve as both the source and system clock. By programming their own specific set of output conditions using the on-chip memory, designers can easily configure the AD9520/2 as the source clock to ensure initial processing functions are synchronized when the system is powered on or reset. Competing clock ICs require a separate source clock, which must be independently matched to the system processor or microcontroller in order to program the system clock chip, adding component count, cost, and complexity to clocking designs. In addition to the on-chip EEPROM and PLL, the AD9520/2 integrates dividers, fanout buffers, and a VCO that tunes from 1.4 GHz to 2.95 GHz. The PLL/VCO clock-generation circuitry boasts industry-leading phase noise, while the clock distribution fanout channels feature ultra-low wideband jitter performance of 225 fs. The AD9520 offers 12 differential LVPECL outputs. The AD9522 includes 12 differential LVDS outputs. The outputs are partitioned in four groups, each with a 1 to 32 divider and phase delay. Both devices alternatively offer up to 24 single-ended CMOS output configurations up to 250 MHz.
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