[Engineering Essentials]
Challenges Lie Ahead At The Physical Layer
High-speed serial data has all but replaced parallel buses, but it's getting tougher to ramp up the throughput.
The physical layer (PHY) of the Open Systems Interconnect (OSI) model conveys the bit stream—electrical impulse, light, or radio signal—through a network. In the context of the OSI model, the PHY embraces the physical as well as the signaling aspects of the interconnect. Here, we will focus just on the electrical issues.
These days, designers are usually most concerned with serial signaling. This came about as data volumes increased and parallel buses just got too wide, cumbersome, and noisy to deal with. Certainly, serial buses aren’t simple, in terms of serializing, deserializing, and clocking. But they have become the dominant communications modality, even for short hops.
One way engineers are trying to meet the demand for greater speed at the physical layer is in the process technologies used for serializer-deserializer (SERDES) functions. This is of particular interest to designers in the fabless semiconductor community who may be considering using a pure-play analog foundry to develop a custom chip. For more on the latest in RF CMOS and silicon-germanium (SiGe) biCMOS, see “Process Technology Considerations For PHY ICs.”
SCALING CHALLENGES On the other hand, according to Allan Evans of Samplify Systems, manufacturers using those advanced semiconductor technologies may be able to focus solely on extending the speed limits for SERDES interfaces. But recent history amply demonstrates that manufacturers that use mainstream CMOS processes face multiple challenges keeping up with increasing line rates, while also simultaneously moving to smaller feature sizes to boost gate density and lower costs (see “Bridging The Data Bandwidth Gap”).
Leading manufacturers in the FPGA market have been continually trying to leapfrog each other with the introduction of each new product family. Yet while Moore’s Law applies directly to shrinking lookup tables with each new process step, high-speed serial interfaces still depend on analog circuit design techniques.
Merely replicating the device models for the analog circuit components is challenge enough for each new process node. To extend the speed of the interfaces, these device models must be improved, which requires an iterative process of circuit redesign, shuttle runs, and characterization.
The Altera Stratix GX family illustrates this obstacle of increasing interface line rates while moving to the next process node. Developed on 130-nm CMOS, the Stratix GX was the first FPGA family to support SERDES interfaces operating at 3.125 Gbits/s.
With the introduction of the Stratix II GX, developed on 90 nm, Altera was able to extend the maximum line rate to 6.25 Gbits/s—quite an achievement. With the Stratix III device developed on 65 nm, though, SERDES interfaces were never made available. Instead, Altera focused its engineering resources to quickly move to 45 nm with the Stratix IV and the SERDES-enabled version, the Stratix IV GX.
By doubling the gate density with each process node, the FPGA capacity increased by a factor of eight from the original Stratix GX. But even at a maximum claimed line speed of 11.3 Gbits/s, the SERDES line rate increased only by a little over a factor of four during the same period from the original 3.125 Gbits/s. Clearly, physical scaling has been challenging. In his sidebar, Evans suggests an alternative approach.
BACK TO BASICS WITH CDR Looking more fundamentally at the engineering essentials associated with extracting information from a non-returnto- zero (NRZ) serial data stream, clock and data recovery (CDR) is accomplished using phase-locked loop (PLL) and delaylocked loop (DLL) circuits. “Clock Recovery Methods for Jitter Analysis,” a Tech Brief from LeCroy, nicely illustrates the basic CDR concept as well as jitter analysis concepts (Fig. 1).
The sampling clock is derived from the data edges by phaselocking to the data transitions. The PLL generates a clock whose jitter follows that of the data for long-term variations in bit rate, but allows short-term variations to pass. The low-pass filter in the PLL feedback loop determines the jitter rates that appear on the recovered sampling clock.
That way, the receiver is unaffected by relatively large changes in the average bit rate that occur over long time periods. The detector uses the recovered clock to determine the presence of a one or zero to locate the symbol boundaries sampling the voltage at the nominal center of the symbol.
In more real-world CDR circuits, though, two separate feedback loops that share a common control voltage track the phase of the input data signal (Fig. 2). A high-speed delay-locked loop path uses a voltage-controlled phase shifter to track the highfrequency components of input jitter.
A separate phase control loop, the voltage-controlled oscillator (VCO), tracks the low-frequency components of input jitter. The VCO’s initial frequency is set by yet a third loop that compares the VCO frequency with the input data frequency and sets the coarse tuning voltage. The jitter-tracking PLL controls the VCO by the fine-tuning control. The delay and phase loops together track the phase of the input data signal.
For example, when the clock lags the input data, the phase detector drives the VCO to a higher frequency and increases the delay through the phase shifter. Both of these actions reduce the phase error between the clock and the data. The faster clock picks up phase, whereas the delayed data loses phase. Because the loop filter is an integrator, the static phase error is driven to 0°.
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