How does the DPD fix that? The solution is to drive the amplifier harder to get more power, which introduces some signal distortion. But if you can predict the type of distortion and then pre-distort the signal in a reverse manner, the distortion is cancelled out. This extends the linear region of the operation range and produces more output power at an efficiency approaching 40%. A smaller amplifier at higher efficiency then can be used with DPD to achieve the desired output power.
To implement the DPD function, the transmitter develops the signal to be transmitted. It is then upconverted and put through a crest factor reduction process before being sent to a DPD process—an algorithm implemented in the FPGA using a combination of DSP elements and a soft processor. But for the algorithm to know how to predistort the signal, it must know what the actual transmitter output looks like.
The PA output is sampled with a directional coupler, amplified, and downconverted to an IF, where it is digitized. The ADC output becomes the feedback the predistortion circuit uses to compute the output signal. This signal then goes to the DAC to be converted to analog and upconverted to the final frequency before it is applied to the PA. The result is a clean, undistorted signal at high power and improved efficiency.
The distortion compensation algorithm is very intricate, as it has to compensate for complex nonlinear interactions and memory effects. The key is to simplify the implementation process as much as possible. This lets engineers achieve the results they need without becoming too embroiled in the algorithmic complexities and saves many hours of development time.
Product Q&A
LTE Now! The evolving Long Term Evolution (LTE) wireless standard being put forth by the 3rd Generation Partnership Project (3GPP) promises to offer higher data speeds for both download and upload transmissions and reduce packet latency on wireless networks. Xilinx has been on the forefront of 3GPP LTE systems development and many of its FPGA products are already used in the advanced development platforms of top-tier wireless equipment manufacturers. To keep pace with the evolution of the standard and deliver the most efficient solutions to support it, Xilinx has introduced new design resources for advanced LTE designs that leverage the performance and flexibility of its Virtex®-5 SXT programmable platform.
LTE DIGITAL FRONT END Xilinx offers a robust development platform for an LTE digital front end (DFE). The solution is made up of a highly optimized set of IP blocks for Digital Up Conversion (DUC), Digital Down Conversion (DDC) and Crest Factor Reduction (CFR) connected together to form a complete LTE radio sub-system. In addition, the DFE design is compatible with existing Digital Pre-Distortion (DPD) designs from Xilinx, enabling systems architects to rapidly implement all the digital system elements necessary for a full performance, commercial LTE system. This development system allows designers to accelerate the design of LTE baseband designs using Xilinx FPGAs and significantly shortens design time compared to using older ASSP and ASIC design methods.
The LTE DFE design is highly configurable and has been architected to support seven single- and multi-carrier scenarios. It provides an optimized solution for each chosen configuration, enabling designers to select the one that meets the targeted system needs, without paying a penalty on design area while helping reduce total system cost and power. The seven scenarios provided are:
• Single-carrier 5-, 10-, 15-, and 20-MHz bandwidths • Dual-carrier 5- and 10-MHz bandwidths • Four-carrier 5-MHz bandwidth
Xilinx programmable platforms allow specific radio designs to be easily customized for 3GPP-LTE. A full suite of easy to use design tools is available, including the Xilinx System Generator for DSP, the industry’s leading tool for designing high performance DSPs.
LTE CHANNEL UPLINK & DOWNLINK For high performance and low latency uplink and downlink, Xilinx supports its LTE solution with optimized IP from its LogiCORE™ library. Its Turbo Encoder and Decoder cores integrate the key functional blocks necessary for a practical LTE baseband channel system, for both the uplink and downlink functions.
Each LogiCORE IP block is controlled via a GUI, using the Xilinx CoregenTM software, which generates a design that is optimized to user-specified parameters. This streamlines development time and verification effort, making integration much simpler. The designs generated by this tool exploit all the features offered through Xilinx XtremeDSPTM technology, resulting in faster performance, reduced power dissipation and lower system latency.
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