[Design View / Design Solution]
Characterizing High-Speed Serial Communications Links Requires Some Analog Savvy
A six-step process helps measure, identify, and eliminate clock and data jitter on those blazing serial signals.
Going back to the serial link being characterized, Figure 13 shows a plot of the jitter spectrum of the TIE taken on the link. In the figure, the spurs present a snapshot of the channel at a specific point in time. The spurs have been numbered F1, F2, F3, and F4 for reference purposes. The first spur is at F1 = 61.44 MHz (the fundamental frequency of the recovered clock). The spurs F2 and F4 are integer multiples (harmonics) of F1. The spur that does not seem to fit in (because there is no clock source on the board with this frequency) is F3 at 153.18 MHz. F3 represents an intermodulation of two or more frequencies on the card. It could also be produced when the high-speed signal crosses over a split in the power/ground plane. When high-speed signals pass over a split reference plane, the discontinuity in the return path for current can create emissions.
Spectral analysis
To reveal sources of jitter, the SI engineer must conduct a spectral analysis of the jitter spectrum plot to get an idea of the modulation frequency of each jitter source. Frequency-domain plots exhibit the unique frequency spurs. You can isolate certain deterministic jitter components using the following methods:
Isolating Periodic Jitter (Pj)
On occasion, the serial data channel will show a nice looking histogram (a Gaussian distribution), yet the spectrum of time interval error (TIE) on the same link shows some spurs. That means a small Pj can be buried in the random jitter and not be visible on the histogram of total jitter. It is therefore worthwhile to do the spectral analysis just so all bases are covered, even when the jitter numbers have not gone out of spec.
In the spectrum plot analysis above, F3 was regarded as the result of an unwanted modulation. It is this type of unwanted modulation (due to EMI or cross-talk, for instance) that usually causes Pj. The signature of period jitter is that it repeats at a fixed frequency. Such unwanted modulation can also be caused by cross-coupling, such as switching noise from the power-supply module coupling into the data or system clock.
Isolating Duty Cycle Distortion (DCD)
DCD points to differences in the rise and fall times of the digital transitions, and to variations in switching thresholds for the devices previously mentioned. DCD is caused by voltage offsets between differential inputs, and by differences in the system rise and fall times. The rise and fall edges in Figure 9, for example, are not aligned in the middle. An SI engineer can attempt to isolate DCD by stimulating the system with a high-frequency pattern such D21.5 (1010101010…). That pattern is effective in exposing DCD while eliminating ISI.
Isolating Inter Symbol Interference (ISI)
A common source of data-dependent jitter (DDj) is the frequency response of the signal path through which the serial data is transmitted. ISI is a type of data-dependent jitter. It is created in the channel line up that includes the cable and connectors, and is affected by losses in the FR4 PCB material. Because ISI is usually the result of a bandwidth limitation in either the transmitter or the signal path, limited rise and fall times in the signals can produce varying amplitudes for the data bits[2]. Another primary source of DDj is impedance mismatch in the channel line up, due to an improper termination of the bus. Reflections caused by a transmission line with mismatched termination impedance can cause delays and/or attenuation of the transmitted signals.
STEP VI: Optimizing Tx Pre-Emphasis And Rx Equalization It’s well established that the amount of attenuation caused by lossy FR4 traces on a PCB depends on the signaling speed and the length of the transmission medium. In short, FR4 losses are more severe at the higher switching frequencies. Pre-emphasis and equalization can mitigate the effects of signal attenuation and degradation, thereby restoring the original signal. This link-optimization step not only applies to designs with PHY devices that support transmitter pre-emphasis and receiver equalization, but also to discrete ICs for pre-emphasis and equalization, which can be used to compensate for the transmission losses caused by FR4 material. This last step of the framework applies to designs that include provision for tuning the pre-emphasis and equalization levels of SERDES/PHY devices. We therefore assume the system in question includes such provisions.
Optimal Pre-Emphasis
Pre-emphasis is a signal-improvement technique that opens the eye pattern at the far end of a cable (at the receiver). In general, pre-emphasis increases the transmitted signal quality by increasing the magnitude of some frequencies with respect to the magnitude of other (usually lower) frequencies. The key is to find the optimal pre-emphasis setting for the design.
For SERDES and PHY devices that support different levels of pre-emphasis, the SI engineer can step through the levels and select the one with the best eye, or the one that achieves a BER of 10–12or better. Also available are pre-emphasis driver ICs (such as the MAX3982 from Maxim) that can be used to optimize performance by manually tuning the transmitter with respect to eye-opening and ISI jitter at the receiver.
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