[Design View / Design Solution]
Characterizing High-Speed Serial Communications Links Requires Some Analog Savvy
A six-step process helps measure, identify, and eliminate clock and data jitter on those blazing serial signals.
One slight advantage of using a discrete pre-emphasis IC versus one that is embedded in a SERDES/PHY device is that the tester can capture an eye diagram at the receiver input, with a scope, and quickly see an improvements in the signal quality. The wider the eye, the better the quality. The SI engineer should therefore look for the best eye opening using the least amount of pre-emphasis. The rule is: don’t over-preemphasize. An optimal setting should provide some improvements in the channel’s overall jitter performance.
Optimal Equalization
Besides adding pre-emphasis, you can also minimize the effects of ISI by optimizing the equalization setting at the receiver. The purpose of the equalizer is to remove and/or overcome the effects of high-frequency attenuation introduced on the waveform while traveling on the PCB and cable. The receive device’s equalizer compensates the received signal for dielectric and skin losses in the PCB material, as well as for high-frequency loss in the cable.
In the practical and experimental sense, the effects of received equalization are difficult to evaluate when that function is embedded in an IC of the SERDES/PHY device. External receiver-equalizer ICs (such as the MAX3784) can provide a way to quickly observe the results of receiver equalization on the scope (as opposed to BER testing for a SERDES). Figure 14shows the MAX3784 equalizer input eye diagram before and after equalization, at a signaling rate of 5 Gbps. These measurements were made on a 40-inch, 6-mil trace (stripline) on FR4 PCB material.
Link performance
While pre-emphasis at the transmitter helps to mitigate interference caused by adjacent symbols in the data, equalization at the receiver can also help to achieve a similar result, as shown in Figure 14. Pre-emphasis and equalization together are the main techniques in use today for reducing or overcoming transmission losses in serial-transmission mediums.
An important question is: how much pre-emphasis and/or equalization is enough? That depends on the application and the channel line-up. Blindly setting the system for too much pre-emphasis or equalization can have negative effects on the system. The SI engineer must take signal-quality measurements to determine the proper amount of pre-emphasis and equalization for a given application. Maxim has a large portfolio of pre-emphasis and equalizer ICs for circuit board and cable applications, covering the range from 1 Gbps (MAX3803) to 12.5 Gbps (MAX3804). For more information, refer to Figure 15 and to www.maxim-ic.com/equalizerSolutions.
If you design a high-speed digital system today, chances are that you will have a jitter spec or a jitter budget to meet. Understanding jitter and its causes allows you to create high-performance systems. The accurate separations of total jitter into random and deterministic jitter, and deterministic jitter into its sub-components (Pj, DCD, ISI), is not only imperative for compliance with the serial standard, but also important in providing diagnostic information for improving the design.
Designers must ensure that their designs work for reasons of competitive advantage, but they must also know the point at which their design stops working. By identifying jitter and its sources, the link-characterization framework proposed in this paper should help to improve system performance (Figure 16).
References:
[1] Jitter fundamentals, “Enhance Speed, Throughput and Accuracy with One Powerful Instrument,” Wavecrest: A Technologies Company, Eden Prairie, Minnesota, available at www.wavecrest.com. [2] A Guide to Understanding and Characterizing Timing Jitter, Tektronix Enabling Innovation Primer, available at www.tektronix.com/jitter.
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