Output results from the tests can show the relationship among hierarchical scan test structure information, data generated by ATPG software, and the traditional table of test vectors applied to the device. With this information, designers can quickly detect and identify erroneous DFT behavior. The tools provided with the Validator allow easy navigation across both structural and tabular views of the same test data.
About the size of a large book, just 350 × 300 × 60 mm, the Validator 500 provides 272 signal pins for testing a chip (see the figure). Of those pins, 256 are used for up to 128 scan chains, eight pins are available for clock driving, and eight pins provide Scan-Enable signals. Inside the system are all the pin electronics to drive the scan chains, clocks, and Scan-Enable signals; software-controllable power supplies; the pattern memory; a 10/100-Mbit/s Ethernet interface; and execution control logic.
On the top of the Validator system are two connectors that provide the interface to a test board that can be plugged directly into the system. The device under test can be socketed on the test board. Or, the board can provide an interface between the Validator and a wafer probe system if you want to check out the chips at the wafer level.
System Specs: Test data can be clocked through the system at 5- to 50-MHz rates (20 to 200 ns), adjustable in 5 ns increments. Clock edge-to-edge accuracy is ±250 ps, while the clocks' pulse placement resolution is 250 ps. DFT data being driven to the device under test has timing set at the transition@cycle boundary (NRZ), while data on the receive side has a strobe placement resolution of 250 ps. The edge placement resolution of the Scan-Enable signal is 250 ps using DNRZ coding. I/O logic levels for the device under test can be set at either 3.3 or 2.5 V, while core supply voltage can be set at any value from 0.7 to 3.8 V.
The Validator comes with DFT-intelligent software that provides an intuitive graphical user interface for easy control of interactive functions. The 10/100-Mbit/s Ethernet port on the Validator links the system to a host computer. The host can typically be a PC that runs Microsoft Windows 2000 and packs 512 Mbytes of RAM, a 1-GHz CPU, a 20-Gbyte hard drive, a 10/100-Mbit/s Ethernet port, and a CD-ROM drive.
The host PC runs the software and controls the Validator over the Ethernet link. Included in the software package are a pattern interface and software modules that provide edit and debug, a structural view, a tabular vector view, and result analysis. Via the software and the graphical user interface, you can quickly and easily adjust device timing and voltage levels and immediately observe the effect of the changes.
The company also is setting up partnerships with major electronic-design-automation tool suppliers to better link the Validator software to design and analysis tools from Synopsys, Mentor Graphics, LogicVison, and other vendors.
Price & Availability
The Validator 500 will be available by the end of this year. The first version of the software performs dc-scan testing, and the hardware/software combination costs about $60,000 (host computer additional). Users will have to create custom device-under-test boards or interfaces to wafer/chip probers.
Teseda Corp., 812 S.W. Washington, 5th floor, Portland, OR 97295-3232; (503) 223-3315; www.teseda.com.
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