[Technology Report]
Wireless-Enabled Systems Challenge Analog/Mixed-Signal Flows
With analog/RF design content rising, designers who have lived in the digital domain must learn to cope. Fortunately, design flows are evolving to make the integration easier.
Circuits such as an automatic gain-control (AGC) circuit can be particularly difficult to simulate, especially when coupled with the control circuitry for a digital-to-analog converter (DAC), says Ouslis. The workaround is to abstract some of the blocks to hide the true circuit-level operation. The tricky part is balancing simulation granularity against exploding runtimes.
Ouslis is a fan of fast-Spice simulators. “There are good tools from vendors such as Berkeley Design Automation, whose fast-Spice tool is very similar to Cadence’s Spectre Turbo, which in turn is similar to HSpice from Synopsys,” he says. Yet even fast-Spice simulators don’t solve all of his issues. “It’s still such a long simulation that you only do it to ensure things are going in the right direction.”
MODELING STILL A VEXING ISSUE As every designer knows all too well, even the best simulators are only as good as the models fed into them. “When analog and/or RF circuitry must be combined with digital logic, the challenge is bridging the two,” says Tom Costas, Cadence’s senior product marketing manager for its Virtuoso product line.
“Even if you treat it more as an envelope simulation than a Spice transient model, it’s still a very large analog simulation problem,” says Richard Davis, corecomp architect at Cadence. “There’s a potential for automating that for certain kinds of circuits. We can build a user interface that will characterize the analog circuit and build a behavioral model that behaves similarly. It’s not identical, but it’s close.” Such envelope simulations run faster than a Spice transient
simulation, says Davis, because you don’t simulate all of the carrier cycles. But it still requires the analog designer to know the circuit well and to set up a testbench. The industry, as a whole, needs to move up in abstraction for analog/mixed-signal work, says Costas. Today, a model must be manually created in the Verilog-A modeling language using a text editor. “You have to be able to follow the language syntax,” says Davis. “Typically, analog designers don’t have the expertise to do that.”
Unfortunately, there is still no complete answer to this problem of how to characterize blocks and build behavioral models with at least some automation. Stabs have been attempted at tools of this nature, but the custom nature of analog circuitry makes their use almost as much work as handcoding the models from scratch. “The biggest stumbling block is that the typical RF designer is not a programmer,” says Davis.
PARASITIC EXTRACTION DRIVES MODELING An important aspect of developing accurate models, of course, is parasitic extraction. Applied Wave Research (AWR) has done a lot of work in this area.
A traditional flow would involve creating a schematic, performing layout and running design-rule checking (DRC) and layout-versus-schematic (LVS) checks, and making sure those respective databases are in sync. Parasitic extraction is then run on the layout. “You can follow that methodology if you wish but we take a different approach,” says Graeme Ritchie, AWR’s Analog Office product manager.”
In AWR’s flow, once you have a schematic, you can begin the process of extraction. “Experience tells you that in some subset of nodes, the parasitics are critical,” Ritchie explains. “Rather than laying out the entire chip or even an entire block, you lay out a few transistors, place and route them, and run parasitic extraction on those interconnects. Those results can then be brought into simulation very early in the design cycle.” The point is to iron out the critical portions before laying out the bulk of the block or chip.
AWR’s ability to approach parasitic extraction in this way is due in part to a unified design database, which tightly links the layout to the schematic. Rather than having two separate databases, the schematic and layout views are simply different views of the unified object-oriented database. “The connectivity is inherently known as soon as you create it in the schematic,” says Ritchie.
In the AWR flow, if only one net is being extracted, the user has a choice of extraction engines depending on the operating frequency and application (Fig. 2). AWR offers three engines: OEA Net-An, an RLCK extractor; AWR ACE, a microwavefrequency extractor; and Axiem, a full 3D planar electromagnetic solver. The choice of extraction engine is as simple as highlighting a net in the schematic and telling the environment which one to use.
“It’s a speed/accuracy tradeoff,” says Ritchie. It’s best to save the 3D EM solver for gnarly things like spiral inductors. But you can choose the right technology for a given application.”
SIMULATORS STILL IMPROVING Once the modeling issues are overcome, the good news is that simulation technology continues to improve. For example, Synopsys recently released its CustomSim circuit simulator, which combines three simulation engines under a single shared license (NanoSim, HSIM, and XA). The result is high-throughput co-simulation with the VCS digital simulator as well as a unified analog/mixed-signal simulation environment with sufficient power and speed for large designs.
Most modern circuit simulators fall into one of two broad categories. There are traditional Spice-based engines such as HSpice, which are highly accurate, “golden” simulator, and there are various flavors of “fast-Spice” simulators, which trade off some accuracy for speed.
“Some circuits, such as PLLs (phaselocked loops) with digital control logic, fall into the gap between these two extremes,” says Graham Etchells, director of product marketing at Synopsys’ AMS Group.
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