[Technology Report]
Wireless-Enabled Systems Challenge Analog/Mixed-Signal Flows
With analog/RF design content rising, designers who have lived in the digital domain must learn to cope. Fortunately, design flows are evolving to make the integration easier.
Synopsys tweaked the three engines to cover these types of circuits that fall between those requiring the accuracy of full Spice and those that do not. Fast transient simulations of PLLs, charge pumps, and regulators run forever in Spice. Synopsys tuned its XA engine to address fast transient simulations, achieving a good compromise between accuracy and speed.
The CustomSim environment also performs what Synopsys terms “native circuit checking,” a process intended to find design errors before tapeout (Fig. 3). “Before launching simulation, we run a battery of electrical rule checks as well as static and dynamic checks on the block or full chip,” says Etchells.
In keeping with the trend of late, Synopsys has also reconfigured the entire Discovery 2009 verification platform to take advantage of multicore hardware architectures. Some of the engines have been rewritten to deliver speedups of up to four times on four-core machines.
In addition, the CustomSim circuit simulator is adept at transistor-level, lowpower verification tasks. It can put a chip or block through its power-up/down sequences, perform static checks for leakage paths, ensure that MT-CMOS devices are correctly configured for safe operation, and determine the impact of IR drop on performance.
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