Inferred link idle: PCCIe places a premium on overall system power. Links that don’t need to carry traffic for prolonged periods (i.e., hundreds of milliseconds) are allowed to orderly quiet the link transmitters. With the link electrically quiet (no data transitions), the receive circuit senses the line and checks if the incoming signal is above approximately 100- to 175-mV EIDLE limit before allowing data to pass beyond the PHY layer. While this is an excellent power-saving feature, as we’ll see later in this article, longer channels and increased data rates mean that valid data could be present below this 175-mV threshold.
Because many of the Gen2 circuits of today and the Gen3 circuits in the non-too-distant future have receiver sensitivities significantly better than EIDLE, the specification now allows for the inference of electrical idle and the exit based on a specific training set sequence that high-quality receivers can detect. Doing so allows PCIe to operate over long/lossy links over which the channel losses can easily reach 20 dB or more (while still saving power when the link isn’t needed).
ACK/NACK protocol: These physical-layer rules are part of another PCIe error-checking and correction mechanism. If an incoming packet has a receiver error (not necessarily a polarity error) such as cyclic redundancy check (CRC), the system provides what’s known as a packet NACK, which forces the transmitting device to resend. If the offending packet is NACKed three times, the link is forced to enter retraining. The ACK/NACK protocol is a powerful error checking and correcting mechanism in PCIe that’s observed by each and every point to point (link) within a system.
De-emphasis: If the physical bandwidth of a given link is less than the required transmit bandwidth, then all of the signal’s frequency components are transported with unequal emphasis—that is, the attenuation of any signal component at the low end of the frequency spectrum will be less than that of the higher portion of the spectrum. Unfortunately, few physical channels maintain a flat amplitude response out past 5 GHz and beyond (optical links are one example, but they have other dispersionary effects). The data bandwidth of high-speed protocols such as PCIe often exceed the bandwidth of most lower-cost PCB materials and/or legacy implementations. However, it’s the ability to deliver higher performance while minimizing the necessity of “forklift” upgrades that’s a critical factor to enabling most backplane applications.
A max loss approximation of a 50-cm, 100-Ω OIF channel is shown (Fig. 5). The channel loss (S21) polynomial is defined in the ANSI FC-Physical Interface specification. The model is first order and not intended to show reflection losses that further diminish the solution space for clean data delivery. As can be seen from the graph, frequency components at the higher end of the data spectrum are more attenuated than lower-frequency components. Two amplitude pulses that are equal, but differ significantly in pulse width, will arrive at the receiver with very different amplitudes.
A time domain example is given of the frequency-dependent loss and reflections due to channel loss and reflections (Fig. 6). A PEX8648 Reference Design Card is operated at 5 Gbits/s. The channel includes multiple PCIe connectors, a PCIe compliance card, SMA to Hz-Md paddle card, and 75c m of backplane operating at 5 Gbits/s.
To show how transmitter de-emphasis provides channel correction, a 5-Gbit/s signal with boosted post cursor (PCIe de-emphasis) is launched into the backplane (Fig. 7). A second plot shows the signal at the end of the backplane (Fig. 8). Both the high- and low-frequency amplitudes are nearly matched after traversing the channel. By minimizing large variations in the instantaneous amplitude feeding the receiver, improved ISI, receiver harmonics, and amplitude-to-phase noise jitter are each better managed and improve the resultant data eye.
SO HOW DOES GEN3 STACK UP?
Conceptually, PCIe Gen3 is simply a doubling of the available data bandwidth over Gen2—from 4 to 8 Gbits/s. Several key differences arise in achieving PCIe Gen3 data rates. To address these differences, we’ll look at several concepts: data rate versus line rate; pulse response; physical-layer architectural decisions, test needs, legacy issues, and equalization architectures and tradeoffs.
Data rate vs. line rate: As discussed previously, PCIe takes eight bits of data and adds two bits of encoding. This results in a 20% overhead in line transmission. The 2.5-Gbit/s line rate of Gen1 has a base data delivery rate of 2 Gbits/s (excluding packet protocol data-link-layer overhead). The PCIe Gen2 5-Gbit/s line rate has a base delivery of 4 Gbits/s. So, for Gen3 to effectively double the speed of Gen2, it’s necessary to deliver a base data rate of 8 Gbits/s.
To do so, Gen3 removes 8b/10b encoding and consequently takes back much of the 20% overhead of encoding. As data rates increase, the premium on usable channel bandwidth also goes up. The rationale for adoption is similar to other protocols looking to reduce overhead (i.e. 64/66b encoding in 10GigE and 10Gig Fibre Channel).
However, with these changes come concerns of clock recovery, data wander, harmonic suppression, and dc balance, as discussed previously. Using the 50-cm OIF channel model as an example, the difference between 4 Gbits/s and 5 Gbits/s is minimally an additional 5 to 6 dB of channel loss that the SERDES would need to resolve. Similarly, with increased speeds comes the likelihood of channel resonance due to discontinuities. These resonances result in additional “dips” in the channel response, which cause distortion and require compensation.
Data Encoding: Rather than 8B/10B, Gen3 will employ alternate encoding that will have a worst-case non-transition period on par with alternate protocols such as 64B/66B encoding. (Actual expectation is a 128-bit pattern with two sync bits.) While something on the order of approximately 64 to 128 bits will be the likely worst-case non-transition period, some means of data scrambling will also be employed.
Without this scrambling, it’s easy to envision types of data streams (e.g., static, uncompressed video) for which ac-coupling and clock recovery could become a problem. With scrambling, chances of obtaining long runs approaching 64 to 128 bits are significantly reduced. The keys to whatever scrambling polynomial(s) are finally chosen include the ability to maintain dc balance, ease of sync, and EMI suppression/balance (see previous section for extreme effects of poor dc balance and data transition).
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