Pulse response analysis: A heuristic discussion of pulse response serves as an aid to visualize the concepts of equalization. Pulse response is an alternate means of channel observation. While S-parameters look at the channel in the frequency domain, pulse response is a means of quantifying a channel in time. An example of what an 8-Gbit/s pulse response might look like entering, then leaving, an arbitrary channel is shown in Figure 9.
At successive time samples, the input pulse has a single non-zero value at one sample instance (0.125 ps), and zero at successive sample points. The output pulse is expected to have some arbitrary delay time commensurate with the propagation delay of the channel. If the channel was ideal, with minimal reflections as well as wide bandwidth and low loss, the resultant output pulse would look much like the input pulse, only shifted in time.
It’s clear that despite a clean input, bandwidth limitations, losses, and discontinuities create pulse spreading (Inter-symbol interference) such that the output response isn’t single valued. The job of equalization is to make the output response as close to single valued (only one non-zero sample point) as possible.
As a visual aid to the potential impact of discontinuities, a 2.5-Gbit/s simulated eye diagram of an ideal transmitter is connected to a 6-in. transmission line (Fig. 10). Within the transmission line model, lumped capacitance is used as a simple via approximation and placed approximately one-third the length of the 6-in. trace (Fig. 11). Alternate simulations show the effect of an additional PCB via and intentional impedance mismatching (Fig. 12).
Used as a simple visual aid, these simulations at 2.5 Gbits/s exhibit how discontinuities create ISI and reduce eye quality both in the horizontal and vertical axis. Channels that behave as such present significant challenges to high-speed data recovery. (We’ll return to pulse response when we discuss various receiver architectures.)
DATA TRANSMISSION AND RECOVERY: ARCHITECTURAL DECISIONS
DLL vs. PLL: Data pattern and anticipated channel behavior plays important roles in defining both the transmitter and receiver design methodologies. For example, the change in data encoding of Gen3 results in longer data run lengths with no transitions. This affects data recovery. Whereas DLL-based clock/data recovery methods (operated with common base reference) are well suited to operate through long transition-less periods, this condition does represent a potential strain on PLL-based data-recovery schemes and requires pre-design verification.
Describing the two architectures, a DLL-based recovery scheme compares the edge of the incoming data stream to one of several quantized phases of a fixed reference. At each data transition, a decision is made as to whether the clock phase or the data edge was first arriving (early/late detection). The early and late counts are accumulated and after a predetermined interval—the counter is effectively the DLL bandwidth—a decision is made to either advance or retard the recovered clock phase.
The key is that if no data transitions occur for an extended period of time, the bandwidth counter doesn’t advance and the clock phase remains unchanged. When the transmitter and receiver at both ends of a link are operated under the condition of a distributed base reference (common in PCIe), CDR tracking can effectively be turned off once data alignment is achieved without incurring data loss.
In contrast, with this same reference clock distribution, a PLL architecture requires spectral content from the data to maintain phase alignment with the incoming reference clock. If no data transitions are present, the charge pump of the PLL will attempt to hold its value. However, it will have a finite time constant, unlike the DLL design. Still, with advances in low leakage design, PLL stability can be tens of bits to potentially more than 100 non-transition bit intervals.
That said, when either of these architectures are operated with asynchronous clocking, both will have a tracking time constant. Thus, it will be important to evaluate the ability to acquire and track under anticipated data densities for each, as well as their maximum frequency offsets.
Transmitter emphasis: If a given channel is continuous but of low bandwidth, data transmission can be improved with more transmitter emphasis to balance the high-frequency losses at the receiver. While post-cursor emphasis has been defined in both PCIe Gen1 and Gen2 (and, eventually in Gen 3), it’s very likely that the best transmitter designs will incorporate something more.
Building off the effort of 10Gig OIF, PCIe Gen3 will likely incorporate a transmit structure capable of both pre- and post-cursor emphasis. (Pre-cursor and post-cursor are becoming the more proper means of defining transmitter emphasis.) Such a structure allows more control and pulse shaping of the launched signal and more flexibility to mitigate crosstalk and reflections in legacy channels. (Refer back to the output response of Figure 9. The non-zero value at 0.125 ns represents the pre-cursor response. Values at 0.375, 500 ns represent successive post-cursors).
In an example three-tap (1 pre, 1 post) transmitter, the tap numbers -1, 0 and +1 refer to the relative position of the signal feeding the summing junction, where Tap(0) is the main (cursor) bit value (Fig. 13). The gain of each tap is independently adjusted, where typically the main tap has a large value (such as approaching “1”) and the side taps are adjustable negative fractional values that subtract from the main tap. Through the investigative work of Liu and others on the 10GBASE-KR equalization specification, precursor adjustability has been shown particularly beneficial to the DFE receive equalization scheme, discussed below. Provided are time representations of PCIe de-emphasis (post cursor) (Fig. 14) and pre- and post-cursor emphasis (Fig. 15).
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