Cynthesizer lets designers choose either SystemC 2.1v1 or the latest SystemC 2.2 release as their design-entry language. Its design-partitioning feature splits the design into multiple parts while automatically determining data dependency between blocks and creating an appropriate interface. Finally, Cynthesizer v3.6 adds an interface-IP generator for design teams to design and create validated, synthesizable interfaces for use in their design.
Cynthesizer v3.6 comes standard with Forte’s TLM synthesis capability, with pricing starting at $275,000. Cynthesizer’s partitioning and interface-generator features start at $40,000 as an add-on to Cynthesizer.
GET AN EARLY DROP ON POWER
As always, getting a handle on power consumption early in the design process is on most designers’ minds. ChipVision Design Systems has enhanced its PowerOpt tool’s capabilities for systemlevel power optimization and has also incorporated significant improvements in language support for designs written in ANSI C, C++, and SystemC. PowerOpt now performs enhanced loop pipelining with automatic run-out support for automatic pipeline flushing. It provides memory access optimizations and eliminates false paths from designs.
Through generation of an SDC constraint file, PowerOpt enables creation of the lowest-power architectures that can be synthesized to gates using RTL synthesis. The latest version also incorporates enhanced clock-gating optimization to determine lowest-power configuration on a register-by-register basis as well as finite state-machine (FSM) encoding that minimizes switching activity to reduce power. The new version of PowerOpt will be available at the end of this month.
On the virtual platform front, CoWare will show its latest electronic system virtualization technologies and how CoWare delivers an executable specification that serves the entire development cycle. CoWare’s tools produce a processor design and implementation of processor model and RTL that can be seamlessly integrated into CoWare Virtual Platform or into FPGA or RTL simulators. They can speed up the architecture design of SoC platforms through early exploration and efficient performance optimization of the interconnect and memory subsystem using ARM AMBA-based virtual platforms.
In the CoWare flow, software development, integration, and test are accomplished through a fully virtualized ARM reference design virtual platform running Google’s Android where the developers can benefit from advanced debugging and software analysis capabilities delivered through Eclipse-based development tools. Lastly, the flow is augmented by processor, interconnect, and peripheral model support representing IP from ARM, MIPS, Renesas, IBM, Tensilica, Toshiba, VeriSilicon, Sonics, and Rambus.
MOVING DOWN IN THE FLOW
In the mainstream design and verification portions of the flow, DAC will showcase a large number of new product and technology introductions. Here are some of the highlights to look for on the show floor and demo suites.
FishTail Design Automation has worked with Texas Instruments to create new technology and a flow for the automated generation of merged-mode design constraints. This work, and its application to a 2 million cell-instance design with more than 30 clocks and 30 operational modes, will be presented in a User Track paper called “The Automated Generation of Merged-Mode Design Constraints.”
The work described in the joint Texas Instruments-FishTail paper at DAC describes the flow, in which a front-end IP design team provides FishTail’s Focus tool a spreadsheet that captures how input ports and configuration registers are programmed in each of the modes (Fig. 2). This mode-table spreadsheet, along with the RTL and clock definitions for the design, are used to automatically generate a super-mode constraint file that correctly constrains the design for a range of operating modes. This flow is applicable for front-end design teams designing new IP blocks.
Satin IP Technologies will be showing its VIP Lane product, which works within customers’ design flows to turn users’ design practices for building IP blocks or whole SoCs into a robust set of quality criteria. VIP Lane automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources, the company claims.
RTL designers are just as power-conscious these days, if not more so, than the system architect working at higher levels of abstraction. To that end, Sequence Design’s PowerArtist-XP combines power analysis and automatic power reduction all within an integrated environment.
The RTL designer, without having to be a power expert, can analyze, monitor, and reduce power consumption in a design from 10% to 50% or more within hours on unfamiliar multi-million instance blocks. A powerful graphical user interface aids power management, enabling the RTL designer to quickly understand where, when, and why power is consumed as well as what precise changes should be made to reduce it.
In other power-analysis-related news, Apache Design Solutions will be showing its Totem, an integrated power- and noiseintegrity platform that addresses the challenges associated with global couplings of power/ground noise, substrate noise, and package/printed-circuit board (PCB) capacitive and inductive noise. Aimed at analog, mixed-signal, memory, and high-speed I/O designs, Totem incorporates transistor-level noise injection, parasitics extraction, package modeling, dynamic analysis, and design debug in a single-flow environment.
Continue on Page 3
Reprints
